A configurable distributed systolic array for QR decomposition in MIMO-OFDM systems. - Yong-xu Zhu; Bin Wu 006; Yumei Zhou; Kaifeng Xia; Lu Sun (ASICON, 2013)

An efficient prime factor memory-based FFT processor for LTE systems. - Kaifeng Xia; Bin Wu 006; Xiaoping Zhou; Tao Xiong (ISCAS, 2016)

A generalized conflict-free address scheme for arbitrary 2k-point memory-based FFT processors. - Kaifeng Xia; Bin Wu 006; Xiaoping Zhou; Tao Xiong (ISCAS, 2016)

Design of a High-Throughput Sliding Block Viterbi Decoder for IEEE 802.11ac WLAN Systems. - Kaifeng Xia; Bin Wu 006; Tao Xiong; Cheng-Ying Chen (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Hardware Efficient Multiple-Stream Pipeline FFT Processor for MIMO-OFDM Systems. - Kaifeng Xia; Bin Wu 006; Tao Xiong; Tian-Chun Ye 001; Cheng-Ying Chen (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes. - Kaifeng Xia; Bin Wu 006; Tao Xiong; Tian-Chun Ye 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)