Hybrid hierarchical timing closure methodology for a high performance and low power DSP. - Kaijian Shi; Graig Godwin (DAC, 2003)

Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs. - Thi Nguyen; Kaijian Shi (ASAP, 2005)

A Clock Isolation Method For Complex SoC Designs. - Kaijian Shi; Hichem Belhadj (SoCC, 2005)

Challenges in sleep transistor design and implementation in low-power designs. - Kaijian Shi; David Howard (DAC, 2006)

Low Power Methodology Manual - for System-on-Chip Design. - Michael Keating; David Flynn; Robert C. Aitken; Alan Gibbons; Kaijian Shi (Springer, 2007)

A Power Network Synthesis Method for Industrial Power Gating Designs. - Kaijian Shi; Zhian Lin; Yi-Min Jiang (ISQED, 2007)

A wakeup rush current and charge-up time analysis method for programmable power-gating designs. - Kaijian Shi; Jingsong Li (SoCC, 2007)

Area and power-delay efficient state retention pulse-triggered flip-flops with scan and reset capabilities. - Kaijian Shi (ICCD, 2008)

Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs. - Kaijian Shi; Zhian Lin; Yi-Min Jiang; Lin Yuan (J. Comput., 2008)

Low-power SOC implementation: What you need to know. - Kaijian Shi (SoCC, 2010)

Well tapping methodologies in power-gating design. - Kaijian Shi; David Tester (SoCC, 2011)

Automation of Switch Insertion and Power Network Generation in 28 nm Power-Switched Designs. - Shane Stelmach; Kaijian Shi; Anthony Hill (J. Low Power Electron., 2012)

Sleep transistor design in 28nm CMOS technology. - Kaijian Shi (SoCC, 2013)

Message from program chairs. - Kaijian Shi; Nagi Naganathan (SoCC, 2013)

Message from conference general chair. - Kaijian Shi (SoCC, 2014)