Kaijie Wu

According to our database1, Kaijie Wu authored at least 76 papers between 2000 and 2018.

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Bibliography

2018
Exploiting Chip Idleness for Minimizing Garbage Collection - Induced Chip Access Conflict on SSDs.
ACM Trans. Design Autom. Electr. Syst., 2018

Potential Trigger Detection for Hardware Trojans.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Exploiting Parallelism for Access Conflict Minimization in Flash-Based Solid State Drives.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Securing Hardware Accelerators: A New Challenge for High-Level Synthesis.
Embedded Systems Letters, 2018

Loss is Gain: Shortening Data for Lifetime Improvement on Low-Cost ECC Enabled Consumer-Level Flash Memory.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Hardware Trojan detection using path delay order encoding with process variation tolerance.
Proceedings of the 23rd IEEE European Test Symposium, 2018

2017
Asymmetric Error Rates of Cell States Exploration for Performance Improvement on Flash Memory Based Storage Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Towards trustworthy storage using SSDs with proprietary FTL.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

Towards Reverse Engineering Reversible Logic.
CoRR, 2017

On the Difficulty of Inserting Trojans in Reversible Computing Architectures.
CoRR, 2017

A PV aware data placement scheme for read performance improvement on LDPC based flash memory: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

2016
Guest Editorial: Real-Time and Embedded Systems.
Signal Processing Systems, 2016

Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems.
IEEE Trans. VLSI Syst., 2016

Retention Trimming for Lifetime Improvement of Flash Memory Storage Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Worst-Case Finish Time Analysis for DAG-Based Applications in the Presence of Transient Faults.
J. Comput. Sci. Technol., 2016

Minimizing cell-to-cell interference by exploiting differential bit impact characteristics of scaled MLC NAND flash memories.
Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016

Access Characteristic Guided Read and Write Cost Regulation for Performance Improvement on Flash Memory.
Proceedings of the 14th USENIX Conference on File and Storage Technologies, 2016

Can flexible, domain specific programmable logic prevent IP theft?
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Exploiting process variation for retention induced refresh minimization on flash memory.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Sharp Corner/Edge Recognition in Domestic Environments Using RGB-D Camera Systems.
IEEE Trans. on Circuits and Systems, 2015

Realistic Task Parallelization of the H.264 Decoding Algorithm for Multiprocessors.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

User Experience Enhanced Task Scheduling and Processor Frequency Scaling for Energy-Sensitive Mobile Devices.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Maximizing IO performance via conflict reduction for flash memory storage systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Towards trustable storage using SSDs with proprietary FTL.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Fault-Duration And-Location Aware CED Technique With Runtime Adaptability.
IEEE Trans. VLSI Syst., 2014

Error Detection and Recovery for ECC: A New Approach Against Side-Channel Attacks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Scan-Based Attack on Stream Ciphers: A Case Study on eSTREAM Finalists.
J. Comput. Sci. Technol., 2014

Efficient fault-tolerant scheduling on multiprocessor systems via replication and deallocation.
IJES, 2014

Messages from the conference chairs.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Energy efficient routing techniques with guaranteed reliability based on multi-level uncertain graph.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Exploiting parallelism in I/O scheduling for access conflict minimization in flash-based solid state drives.
Proceedings of the IEEE 30th Symposium on Mass Storage Systems and Technologies, 2014

Exploit asymmetric error rates of cell states to improve the performance of flash memory storage systems.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Retention Trimming for Wear Reduction of Flash Memory Storage Systems.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

High-Level Synthesis for Run-Time Hardware Trojan Detection and Recovery.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Efficient feasibility analysis of DAG scheduling with real-time constraints in the presence of faults.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A method for construction of Nitinol antenna for implantable medical devices.
Proceedings of the 6th International Conference on Biomedical Engineering and Informatics, 2013

2012
Homomorphic Property-Based Concurrent Error Detection of RSA: A Countermeasure to Fault Attack.
IEEE Trans. Computers, 2012

Quasi-static fault-tolerant scheduling schemes for energy-efficient hard real-time systems.
Journal of Systems and Software, 2012

2011
Scan-based attacks on linear feedback shift register based stream ciphers.
ACM Trans. Design Autom. Electr. Syst., 2011

Runtime adaptable concurrent error detection for linear digital systems.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

LOEDAR: A low cost error detection and recovery scheme for ECC.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Towards cool and reliable digital systems: RT level CED techniques with runtime adaptability.
Proceedings of the 28th International Conference on Computer Design, 2010

Scheduling for energy efficiency and fault tolerance in hard real-time systems.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Scan-based Attacks on Linear Feedback Shift Register Based Stream Ciphers.
IACR Cryptology ePrint Archive, 2009

An ILP formulation to Unify Power Efficiency and Fault Detection at Register-Transfer Level.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
Fixed-Priority Allocation and Scheduling for Energy-Efficient Fault Tolerance in Hard Real-Time Multiprocessor Systems.
IEEE Trans. Parallel Distrib. Syst., 2008

2007
The Robust QCA Adder Designs Using Composable QCA Building Blocks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique.
IEEE Trans. Computers, 2007

Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations.
Proceedings of the Fourth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2007

2006
Secure Scan: A Design-for-Test Architecture for Crypto Chips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks.
IEEE Trans. Computers, 2006

Quantum-Dot Cellular Automata Design Guideline.
IEICE Transactions, 2006

Online task-scheduling for fault-tolerant low-energy real-time systems.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005
Towards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths.
Proceedings of the 2005 Design, 2005

Secure scan: a design-for-test architecture for crypto chips.
Proceedings of the 42nd Design Automation Conference, 2005

Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Fault secure datapath synthesis using hybrid time and hardware redundancy.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Scan Based Side Channel Attack on Data Encryption Standard.
IACR Cryptology ePrint Archive, 2004

Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Low Cost Concurrent Error Detection for the Advanced Encryption Standard.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Concurrent Error Detection Schemes for Involution Ciphers.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2004

2003
Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths.
IEEE Trans. Reliability, 2003

Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher.
Microelectronics Journal, 2003

Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique.
IEEE Trans. VLSI Syst., 2002

Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Exploiting Idle Cycles for Algorithm Level Re-Computing.
Proceedings of the 2002 Design, 2002

2001
Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Idle Cycles Based Concurrent Error Detection of RC6 Encryption.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers.
Proceedings of the 38th Design Automation Conference, 2001

2000
Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000


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