Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique. - Ramesh Karri; Kaijie Wu 001 (ITC, 2000)

Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers. - Ramesh Karri; Kaijie Wu 001; Piyush Mishra; Yongkook Kim (DAC, 2001)

Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture. - Ramesh Karri; Kaijie Wu 001; Piyush Mishra; Yongkook Kim (DFT, 2001)

Idle Cycles Based Concurrent Error Detection of RC6 Encryption. - Kaijie Wu 001; Ramesh Karri (DFT, 2001)

Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique. - Kaijie Wu 001; Ramesh Karri (ICCAD, 2001)

Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique. - Kaijie Wu 001; Ramesh Karri (ITC, 2001)

Exploiting Idle Cycles for Algorithm Level Re-Computing. - Kaijie Wu 001; Ramesh Karri (DATE, 2002)

Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers. - Ramesh Karri; Kaijie Wu 001; Piyush Mishra; Yongkook Kim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection. - Kaijie Wu 001; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique. - Ramesh Karri; Kaijie Wu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis. - Kaijie Wu 001; Ramesh Karri (ITC, 2003)

Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher. - Kaijie Wu 001; Piyush Mishra; Ramesh Karri (Microelectron. J., 2003)

Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths. - Kaijie Wu 001; Ramesh Karri (IEEE Trans. Reliab., 2003)

Concurrent Error Detection Schemes for Involution Ciphers. - Nikhil Joshi; Kaijie Wu 001; Ramesh Karri (CHES, 2004)

Low Cost Concurrent Error Detection for the Advanced Encryption Standard. - Kaijie Wu 001; Ramesh Karri; Grigori Kuznetsov; Michael Gössel (ITC, 2004)

Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard. - Bo Yang 010; Kaijie Wu 001; Ramesh Karri (ITC, 2004)

Scan Based Side Channel Attack on Data Encryption Standard. - Bo Yang 010; Kaijie Wu 001; Ramesh Karri (IACR Cryptol. ePrint Arch., 2004)

Fault secure datapath synthesis using hybrid time and hardware redundancy. - Kaijie Wu 001; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands. - Tongquan Wei; Kaijie Wu 001; Ramesh Karri; Alex Orailoglu (ASP-DAC, 2005)

Towards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths. - Kyosun Kim; Kaijie Wu 001; Ramesh Karri (DATE, 2005)

Online task-scheduling for fault-tolerant low-energy real-time systems. - Tongquan Wei; Piyush Mishra; Kaijie Wu 001; Han Liang (ICCAD, 2006)

Quantum-Dot Cellular Automata Design Guideline. - Kyosun Kim; Kaijie Wu 001; Ramesh Karri (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks. - Nikhil Joshi; Jayachandran Sundararajan; Kaijie Wu 001; Bo Yang 010; Ramesh Karri (IEEE Trans. Computers, 2006)

Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design. - Nikhil Joshi; Kaijie Wu 001; Jayachandran Sundararajan; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique. - Kaijie Wu 001; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Secure Scan: A Design-for-Test Architecture for Crypto Chips. - Bo Yang 010; Kaijie Wu 001; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations. - Richard Stern; Nikhil Joshi; Kaijie Wu 001; Ramesh Karri (FDTC, 2007)

Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique. - Han Liang; Piyush Mishra; Kaijie Wu 001 (IEEE Trans. Computers, 2007)

The Robust QCA Adder Designs Using Composable QCA Building Blocks. - Kyosun Kim; Kaijie Wu 001; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Fixed-Priority Allocation and Scheduling for Energy-Efficient Fault Tolerance in Hard Real-Time Multiprocessor Systems. - Tongquan Wei; Piyush Mishra; Kaijie Wu 001; Han Liang (IEEE Trans. Parallel Distributed Syst., 2008)

An ILP formulation to Unify Power Efficiency and Fault Detection at Register-Transfer Level. - Yu Liu; Kaijie Wu 001 (DFT, 2009)

Scheduling for energy efficiency and fault tolerance in hard real-time systems. - Yu Liu; Han Liang; Kaijie Wu 001 (DATE, 2010)

Towards cool and reliable digital systems: RT level CED techniques with runtime adaptability. - Yu Liu; Kaijie Wu 001 (ICCD, 2010)

LOEDAR: A low cost error detection and recovery scheme for ECC. - Kun Ma; Kaijie Wu 001 (DATE, 2011)

Runtime adaptable concurrent error detection for linear digital systems. - Yu Liu; Kaijie Wu 001 (ICCD, 2011)

Scan-based attacks on linear feedback shift register based stream ciphers. - Yu Liu; Kaijie Wu 001; Ramesh Karri (ACM Trans. Design Autom. Electr. Syst., 2011)

Quasi-static fault-tolerant scheduling schemes for energy-efficient hard real-time systems. - Tongquan Wei; Piyush Mishra; Kaijie Wu 001; Junlong Zhou (J. Syst. Softw., 2012)

Homomorphic Property-Based Concurrent Error Detection of RSA: A Countermeasure to Fault Attack. - Kun Ma; Han Liang; Kaijie Wu 001 (IEEE Trans. Computers, 2012)

A method for construction of Nitinol antenna for implantable medical devices. - Kaijie Wu 001; Shawn Patrick Casey; Lei Zhao; Xinyu Chai (BMEI, 2013)

Efficient feasibility analysis of DAG scheduling with real-time constraints in the presence of faults. - Xiaotong Cui; Jun Zhang; Kaijie Wu 001; Edwin Hsing-Mean Sha (ASP-DAC, 2014)

High-Level Synthesis for Run-Time Hardware Trojan Detection and Recovery. - Xiaotong Cui; Kun Ma; Liang Shi 001; Kaijie Wu 001 (DAC, 2014)

Retention Trimming for Wear Reduction of Flash Memory Storage Systems. - Liang Shi 001; Kaijie Wu 001; Mengying Zhao; Chun Jason Xue; Edwin Hsing-Mean Sha (DAC, 2014)

Exploit asymmetric error rates of cell states to improve the performance of flash memory storage systems. - Congming Gao; Liang Shi 001; Kaijie Wu 001; Chun Jason Xue; Edwin Hsing-Mean Sha (ICCD, 2014)

Exploiting parallelism in I/O scheduling for access conflict minimization in flash-based solid state drives. - Congming Gao; Liang Shi 001; Mengying Zhao; Chun Jason Xue; Kaijie Wu 001; Edwin Hsing-Mean Sha (MSST, 2014)

Energy efficient routing techniques with guaranteed reliability based on multi-level uncertain graph. - Wendi Nie; Yaoxin Duan; Kaijie Wu 001; Qingfeng Zhuge; Edwin Hsing-Mean Sha (RTCSA, 2014)

Messages from the conference chairs. - Edwin Hsing-Mean Sha; Jörg Henkel; Kaijie Wu 001; Tarek F. Abdelzaher; Hojung Cha (RTCSA, 2014)

Efficient fault-tolerant scheduling on multiprocessor systems via replication and deallocation. - Jun Zhang; Edwin Hsing-Mean Sha; Qingfeng Zhuge; Juan Yi; Kaijie Wu 001 (Int. J. Embed. Syst., 2014)

Scan-Based Attack on Stream Ciphers: A Case Study on eSTREAM Finalists. - Minhui Zou; Kun Ma; Kaijie Wu 001; Edwin Hsing-Mean Sha (J. Comput. Sci. Technol., 2014)

Error Detection and Recovery for ECC: A New Approach Against Side-Channel Attacks. - Kun Ma; Kaijie Wu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Fault-Duration And-Location Aware CED Technique With Runtime Adaptability. - Yu Liu; Kaijie Wu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Towards trustable storage using SSDs with proprietary FTL. - Xiaotong Cui; Minhui Zou; Liang Shi 001; Kaijie Wu 001 (DATE, 2015)

Maximizing IO performance via conflict reduction for flash memory storage systems. - Qiao Li 001; Liang Shi 001; Congming Gao; Kaijie Wu 001; Chun Jason Xue; Qingfeng Zhuge; Edwin Hsing-Mean Sha (DATE, 2015)

User Experience Enhanced Task Scheduling and Processor Frequency Scaling for Energy-Sensitive Mobile Devices. - Jie Dai; Weichen Liu; Xiaohao Lin; Yaoyao Ye; Chunming Xiao; Kaijie Wu 001; Qingfeng Zhuge; Edwin Hsing-Mean Sha (HPCC/CSS/ICESS, 2015)

Realistic Task Parallelization of the H.264 Decoding Algorithm for Multiprocessors. - Xiaohao Lin; Weichen Liu; Chunming Xiao; Jie Dai; Xianlu Luo; Dan Zhang 011; Duo Liu; Kaijie Wu 001; Qingfeng Zhuge; Edwin Hsing-Mean Sha (HPCC/CSS/ICESS, 2015)

Sharp Corner/Edge Recognition in Domestic Environments Using RGB-D Camera Systems. - Junlong Zhou; Jianming Yan; Tongquan Wei; Kaijie Wu 001; Xiaodao Chen; Shiyan Hu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Exploiting process variation for retention induced refresh minimization on flash memory. - Yejia Di; Liang Shi 001; Kaijie Wu 001; Chun Jason Xue (DATE, 2016)

Can flexible, domain specific programmable logic prevent IP theft? - Xiaotong Cui; Kaijie Wu 001; Siddharth Garg; Ramesh Karri (DFT, 2016)

Access Characteristic Guided Read and Write Cost Regulation for Performance Improvement on Flash Memory. - Qiao Li 001; Liang Shi 001; Chun Jason Xue; Kaijie Wu 001; Cheng Ji 002; Qingfeng Zhuge; Edwin Hsing-Mean Sha (FAST, 2016)

Minimizing cell-to-cell interference by exploiting differential bit impact characteristics of scaled MLC NAND flash memories. - Yejia Di; Liang Shi 001; Congming Gao; Kaijie Wu 001; Chun Jason Xue; Edwin Hsing-Mean Sha (NVMSA, 2016)

Worst-Case Finish Time Analysis for DAG-Based Applications in the Presence of Transient Faults. - Xiaotong Cui; Kaijie Wu 001; Tongquan Wei; Edwin Hsing-Mean Sha (J. Comput. Sci. Technol., 2016)

Retention Trimming for Lifetime Improvement of Flash Memory Storage Systems. - Liang Shi 001; Kaijie Wu 001; Mengying Zhao; Chun Jason Xue; Duo Liu; Edwin Hsing-Mean Sha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems. - Liang Shi 001; Yejia Di; Mengying Zhao; Chun Jason Xue; Kaijie Wu 001; Edwin Hsing-Mean Sha (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Guest Editorial: Real-Time and Embedded Systems. - Kaijie Wu 001; Zili Shao (J. Signal Process. Syst., 2016)

A PV aware data placement scheme for read performance improvement on LDPC based flash memory: work-in-progress. - Qiao Li 001; Liang Shi 001; Yejia Di; Yajuan Du; Kaijie Wu 001; Chun Jason Xue; Qingfeng Zhuge; Edwin Hsing-Mean Sha (CODES+ISSS, 2017)

Towards Reverse Engineering Reversible Logic. - Samah Mohamed Saeed; Xiaotong Cui; Robert Wille; Alwin Zulehner; Kaijie Wu 001; Rolf Drechsler; Ramesh Karri (CoRR, 2017)

面向内存文件系统的数据一致性更新机制研究 (Research on Data Consistency for In-memory File Systems). - Zhilong Sun; Edwin H.-M. Sha; Qingfeng Zhuge; Xianzhang Chen; Kaijie Wu 001 (计算机科学, 2017)

Towards trustworthy storage using SSDs with proprietary FTL. - Xiaotong Cui; Liang Shi 001; Kaijie Wu 001 (Microprocess. Microsystems, 2017)

Asymmetric Error Rates of Cell States Exploration for Performance Improvement on Flash Memory Based Storage Systems. - Edwin Hsing-Mean Sha; Congming Gao; Liang Shi 001; Kaijie Wu 001; Mengying Zhao; Chun Jason Xue (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Hardware Trojan detection using path delay order encoding with process variation tolerance. - Xiaotong Cui; Kaijie Wu 001; Ramesh Karri (ETS, 2018)

Loss is Gain: Shortening Data for Lifetime Improvement on Low-Cost ECC Enabled Consumer-Level Flash Memory. - Yejia Di; Liang Shi 001; Congming Gao; Qiao Li 001; Kaijie Wu 001; Chun Jason Xue (ACM Great Lakes Symposium on VLSI, 2018)

IC/IP piracy assessment of reversible logic. - Samah Mohamed Saeed; Xiaotong Cui; Alwin Zulehner; Robert Wille; Rolf Drechsler; Kaijie Wu 001; Ramesh Karri (ICCAD, 2018)

Securing Hardware Accelerators: A New Challenge for High-Level Synthesis. - Christian Pilato; Siddharth Garg; Kaijie Wu 001; Ramesh Karri; Francesco Regazzoni 001 (IEEE Embed. Syst. Lett., 2018)

Hardware Trojan Detection Using the Order of Path Delay. - Xiaotong Cui; Elnaz Koopahi; Kaijie Wu 001; Ramesh Karri (ACM J. Emerg. Technol. Comput. Syst., 2018)

Exploiting Parallelism for Access Conflict Minimization in Flash-Based Solid State Drives. - Congming Gao; Liang Shi 001; Cheng Ji 002; Yejia Di; Kaijie Wu 001; Chun Jason Xue; Edwin Hsing-Mean Sha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Potential Trigger Detection for Hardware Trojans. - Minhui Zou; Xiaotong Cui; Liang Shi 001; Kaijie Wu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Exploiting Chip Idleness for Minimizing Garbage Collection - Induced Chip Access Conflict on SSDs. - Congming Gao; Liang Shi 001; Yejia Di; Qiao Li 001; Chun Jason Xue; Kaijie Wu 001; Edwin Hsing-Mean Sha (ACM Trans. Design Autom. Electr. Syst., 2018)

Split Manufacturing-Based Register Transfer-Level Obfuscation. - Xiaotong Cui; Jeff Jun Zhang; Kaijie Wu 001; Siddharth Garg; Ramesh Karri (ACM J. Emerg. Technol. Comput. Syst., 2019)

Minimizing Retention Induced Refresh Through Exploiting Process Variation of Flash Memory. - Yejia Di; Liang Shi 001; Congming Gao; Qiao Li 001; Chun Jason Xue; Kaijie Wu 001 (IEEE Trans. Computers, 2019)

TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking. - Christian Pilato; Kaijie Wu 001; Siddharth Garg; Ramesh Karri; Francesco Regazzoni 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

On the Difficulty of Inserting Trojans in Reversible Computing Architectures. - Xiaotong Cui; Samah Mohamed Saeed; Alwin Zulehner; Robert Wille; Kaijie Wu 001; Rolf Drechsler; Ramesh Karri (IEEE Trans. Emerg. Top. Comput., 2020)

Toward Building and Optimizing Trustworthy Systems Using Untrusted Components: A Graph-Theoretic Perspective. - Xiaotong Cui; Xing Zhang; Hao Yan; Liang Zhang; Kefei Cheng; Yu Wu 001; Kaijie Wu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)