Power analysis for two-stage high resolution pipeline SAR ADC. - Kairang Chen; Quoc-Tai Duong; Atila Alvandpour (MIXDES, 2015)

Capacitive charge pump gain-stage with source follower buffers for pipelined SAR ADCs. - Kairang Chen; Atila Alvandpour (ISIC, 2016)

Design of a gain-stage for pipelined SAR ADC using capacitive charge pump. - Kairang Chen; Atila Alvandpour (MIXDES, 2016)

Asynchronous clock generator for a 14-bit two-stage pipelined SAR ADC in 0.18 μm CMOS. - Kairang Chen; Martin Nielsen-Lönn; Atila Alvandpour (NORCAS, 2016)

A Linearity-Improved 8-bit 320-MS/s SAR ADC With Metastability Immunity Technique. - Daiguo Xu; Lei Qiu 002; Zhengping Zhang; Tao Liu; Lu Liu; Kairang Chen; Shiliu Xu (IEEE Trans. Very Large Scale Integr. Syst., 2018)

On First-Order Compensation of Timing Mismatch in Two-Channel TIADCs. - Yinan Wang; Xiangyu Liu; Håkan Johansson; Chengxuan Zhao; Kairang Chen; Xi Zhu (ISCAS, 2020)