ArchNet: Data Hiding Model in Distributed Machine Learning System. - Kaiyan Chang; Wei Jiang 016; Zicheng Gong; Xiangyu Wen; Zhiyuan He 001; Weijia Pan (CoRR, 2020)

ArchNet: A data hiding design for distributed machine learning systems. - Kaiyan Chang; Wei Jiang 016; Jinyu Zhan; Zicheng Gong; Weijia Pan (J. Syst. Archit., 2021)

Full State Quantum Circuit Simulation Beyond Memory Limit. - Yilun Zhao 002; Yu Chen; He Li; Ying Wang 001; Kaiyan Chang; Bingmeng Wang; Bing Li 017; Yinhe Han 001 (ICCAD, 2023)

ChipGPT: How far are we from natural language hardware design. - Kaiyan Chang; Ying Wang 001; Haimeng Ren; Mengdi Wang 004; Shengwen Liang; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

Learning Evaluation Models from Large Language Models for Sequence Generation. - Chenglong Wang 002; Hang Zhou; Kaiyan Chang; Tongran Liu; Chunliang Zhang; Quan Du; Tong Xiao; Jingbo Zhu (CoRR, 2023)

Hybrid Alignment Training for Large Language Models. - Chenglong Wang 002; Hang Zhou; Kaiyan Chang; Bei Li; Yongyu Mu; Tong Xiao; Tongran Liu; JingBo Zhu (ACL (Findings), 2024)

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. - Kaiyan Chang; Kun Wang 055; Nan Yang; Ying Wang 001; Dantong Jin; Wenlong Zhu; Zhirong Chen; Cangyuan Li; Hao Yan; Yunhao Zhou; Zhuoliang Zhao; Yuan Cheng; et al. (DAC, 2024)

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. - Kaiyan Chang; Zhirong Chen; Yunhao Zhou; Wenlong Zhu; Kun Wang 055; Haobo Xu; Cangyuan Li; Mengdi Wang 004; Shengwen Liang; Huawei Li 001; Yinhe Han 001; Ying Wang 001 (ICCAD, 2024)

Efficient Prompting Methods for Large Language Models: A Survey. - Kaiyan Chang; Songcheng Xu; Chenglong Wang 002; Yingfeng Luo; Tong Xiao; Jingbo Zhu (CoRR, 2024)

RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework. - Kun Wang 055; Kaiyan Chang; Mengdi Wang 004; Xingqi Zou; Haobo Xu; Yinhe Han 001; Ying Wang 001 (ASP-DAC, 2025)

RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework. - Kun Wang 055; Kaiyan Chang; Mengdi Wang 004; Xinqi Zou; Haobo Xu; Yinhe Han 001; Ying Wang 001 (CoRR, 2025)

Large Processor Chip Model. - Kaiyan Chang; Mingzhi Chen; Yunji Chen; Zhirong Chen; Dongrui Fan; Junfeng Gong; Nan Guo; Yinhe Han 001; Qinfen Hao; Shuo Hou; Xuanjing Huang 001; Pengwei Jin; et al. (CoRR, 2025)

ChipSeek-R1: Generating Human-Surpassing RTL with LLM via Hierarchical Reward-Driven Reinforcement Learning. - Zhirong Chen; Kaiyan Chang; Zhuolin Li; Xinyang He; Chujie Chen; Cangyuan Li; Mengdi Wang 004; Haobo Xu; Yinhe Han 001; Ying Wang 001 (CoRR, 2025)

Step-level Verifier-guided Hybrid Test-Time Scaling for Large Language Models. - Kaiyan Chang; Yonghao Shi; Chenglong Wang 002; Hang Zhou; Chi Hu; Xiaoqian Liu; Yingfeng Luo; Yuan Ge 001; Tong Xiao; Jingbo Zhu (CoRR, 2025)

One Size Does Not Fit All: A Distribution-Aware Sparsification for More Precise Model Merging. - Yingfeng Luo; Dingyang Lin; Junxin Wang; Ziqiang Xu; Kaiyan Chang; Tong Zheng; Bei Li; Anxiang Ma; Tong Xiao; Zhengtao Yu 001; Jingbo Zhu (CoRR, 2025)

LLMulator: Generalizable Cost Modeling for Dataflow Accelerators with Input-Adaptive Control Flow. - Kaiyan Chang; Wenlong Zhu; Shengwen Liang; Huawei Li 001; Ying Wang 001 (CoRR, 2025)

SUBQRAG: Sub-Question Driven Dynamic Graph RAG. - Jiaoyang Li; Junhao Ruan; Shengwei Tang; Saihan Chen; Kaiyan Chang; Yuan Ge 001; Tong Xiao; Jingbo Zhu (CoRR, 2025)

A data-centric chip design agent framework for Verilog code generation. - Kaiyan Chang; Wenlong Zhu; Kun Wang 055; Xinyang He; Nan Yang; Zhirong Chen; Dantong Jin; Cangyuan Li; Yunhao Zhou; Hao Yan; Zhuoliang Zhao; Yuan Cheng; et al. (ACM Trans. Design Autom. Electr. Syst., 2025)

AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models. - Cangyuan Li; Chujie Chen; Yudong Pan; Wenjun Xu; Yiqi Liu; Kaiyan Chang; Yujie Wang; Mengdi Wang 004; Huawei Li 001; Yinhe Han 001; Ying Wang 001 (ACM Trans. Design Autom. Electr. Syst., 2025)