A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry. - Eric Karl; Yih Wang; Yong-Gee Ng; Zheng Guo; Fatih Hamzaoglu; Uddalak Bhattacharya; Kevin Zhang 001; Kaizad Mistry; Mark Bohr (ISSCC, 2012)

A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry. - Eric Karl; Yih Wang; Yong-Gee Ng; Zheng Guo; Fatih Hamzaoglu; Mesut Meterelliyoz; John Keane 001; Uddalak Bhattacharya; Kevin Zhang 001; Kaizad Mistry; Mark Bohr (IEEE J. Solid State Circuits, 2013)

Keynote Address 1: "Transistors and reliability in the innovation era". - Kaizad Mistry (IRPS, 2015)

8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET. - P. Mishra; A. Tan; Belal Helal; Cheng-Ru Ho; C. Loi; Jamal Riani; J. Sun; Kaizad Mistry; Karthik Raviprakash; L. Tse; M. Davoodi; M. Takefman; et al. (ISSCC, 2021)