A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing. - Yasunobu Nakase; Kakutaro Suda; Koichiro Mashiko; Tatsuhiko Ikeda; Shinpei Kayano (IEEE J. Solid State Circuits, 1991)

A 64-bit carry look ahead adder using pass transistor BiCMOS gates. - Kiniio Ueda; Hiroaki Suzuki; Kakutaro Suda; Hirofumi Shinohara; Koichiro Mashiko (IEEE J. Solid State Circuits, 1996)