Highly parallel decoding of space-time codes on graphics processing units. - Kalyana C. Bollapalli; Yiyue Wu; Kanupriya Gulati; Sunil P. Khatri; A. Robert Calderbank (Allerton, 2009)

Low power and high performance sram design using bank-based selective forward body bias. - Kalyana C. Bollapalli; Rajesh Garg; Kanupriya Gulati; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2009)

On-chip bidirectional wiring for heavily pipelined systems using network coding. - Kalyana C. Bollapalli; Rajesh Garg; Kanupriya Gulati; Sunil P. Khatri (ICCD, 2009)

A PLL design based on a standing wave resonant oscillator. - Vinay Karkala; Kalyana C. Bollapalli; Rajesh Garg; Sunil P. Khatri (ICCD, 2009)

A robust pulsed flip-flop and its use in enhanced scan design. - Rajesh Kumar; Kalyana C. Bollapalli; Rajesh Garg; Tarun Soni; Sunil P. Khatri (ICCD, 2009)

Selective Forward Body Bias for High Speed and Low Power SRAMs. - Kalyana C. Bollapalli; Rajesh Garg; Kanupriya Gulati; Sunil P. Khatri (J. Low Power Electron., 2009)

Implementing digital logic with sinusoidal supplies. - Kalyana C. Bollapalli; Sunil P. Khatri; Laszlo B. Kish (DATE, 2010)

An Automated Approach for Minimum Jitter Buffered H-Tree Construction. - Ayan Mandal; Nikhil Jayakumar; Kalyana C. Bollapalli; Sunil P. Khatri; Rabi N. Mahapatra (VLSI Design, 2011)

A low-jitter phase-locked resonant clock generation and distribution scheme. - Ayan Mandal; Kalyana C. Bollapalli; Nikhil Jayakumar; Sunil P. Khatri; Rabi N. Mahapatra (ICCD, 2013)