An ultrasonic volumetric scanner for image-guided surgery. - Jeremy Johnson; Ömer Oralkan; Kambiz Kaviani; Utkan Demirci; Mustafa Karaman; Pierre Khuri-Yakub (CARS, 2001)

A multichannel pipeline analog-to-digital converter for an integrated 3-D ultrasound imaging system. - Kambiz Kaviani; Ömer Oralkan; Pierre Khuri-Yakub; Bruce A. Wooley (IEEE J. Solid State Circuits, 2003)

Clocking circuits for a 16Gb/s memory interface. - Ting Wu 003; Xudong Shi 004; Kambiz Kaviani; Haechang Lee; Jung-Hoon Chun; T. J. Chin; Jie Shen 010; Rich Perego; Ken Chang (CICC, 2008)

A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface. - Haechang Lee; Kun-Yung Ken Chang; Jung-Hoon Chun; Ting Wu 003; Yohan Frans; Brian S. Leibowitz; Nhat Nguyen; T. J. Chin; Kambiz Kaviani; Jie Shen 010; Xudong Shi 004; Wendemagegnehu T. Beyene; et al. (IEEE J. Solid State Circuits, 2009)

A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching. - Masum Hossain; Kambiz Kaviani; Barry Daly; Makarand Shirasgaonkar; Wayne D. Dettloff; Teva Stone; Kashinath Prabhu; Brian Tsang; John C. Eble; Jared Zerbe (CICC, 2012)

A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS. - Kambiz Kaviani; Masum Hossain; Meisam Honarvar Nazari; Fred Heaton; Jihong Ren; Jared Zerbe (CICC, 2012)

A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link. - Amir Amirkhany; Kambiz Kaviani; Ali-Azam Abbasfar; H. Md. Shuaeb Fazeel; Wendemagegnehu T. Beyene; Chikara Hoshino; Chris J. Madden; Ken Chang; Chuck Yuan (ISSCC, 2012)

A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration. - Kambiz Kaviani; Amir Amirkhany; Charlie Huang; Phuong Le; Chris J. Madden; Keisuke Saito; Koji Sano; Vinod Murugan; Wendemagegnehu T. Beyene; Ken Chang; Chuck Yuan (ISSCC, 2012)

A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link. - Amir Amirkhany; Kambiz Kaviani; Ali-Azam Abbasfar; H. Md. Shuaeb Fazeel; Wendemagegnehu T. Beyene; Chikara Hoshino; Chris J. Madden; Ken Chang; Chuck Yuan (IEEE J. Solid State Circuits, 2012)

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface. - Amir Amirkhany; Jason Wei; Navin K. Mishra; Jie Shen 010; Wendemagegnehu T. Beyene; Catherine Chen 005; T. J. Chin; Deborah Dressler; Charlie Huang; Vijay P. Gadde; Mohammad Hekmat; Kambiz Kaviani; et al. (IEEE J. Solid State Circuits, 2012)

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. - Kambiz Kaviani; Ting Wu 003; Jason Wei; Amir Amirkhany; Jie Shen 010; T. J. Chin; Chintan Thakkar; Wendemagegnehu T. Beyene; Norman Chan; Catherine Chen 005; Bing Ren Chuang; Deborah Dressler; et al. (IEEE J. Solid State Circuits, 2012)

A 0.94mW/Gb/s 22Gb/s 2-tap partial-response DFE receiver in 40nm LP CMOS. - Kwangmo Jung; Amir Amirkhany; Kambiz Kaviani (ISSCC, 2013)

A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems. - Kambiz Kaviani; Michael Bucher; Bruce Su; Barry Daly; Bill Stonecypher; Wayne D. Dettloff; Teva Stone; Kashinath Prabhu; Pravin Kumar Venkatesan; Fred Heaton; Ravi T. Kollipara; Yi Lu; et al. (ISSCC, 2013)

A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver. - Kambiz Kaviani; Amir Amirkhany; Charlie Huang; Phuong Le; Wendemagegnehu T. Beyene; Chris J. Madden; Keisuke Saito; Koji Sano; Vinod Inipodu Murugan; Kun-Yung Ken Chang; Xingchao Chuck Yuan (IEEE J. Solid State Circuits, 2013)

An Adaptive Body-Biased Clock Generation System in 28nm CMOS. - Makarand Shirasgaonkar; Roxanne Vu; Deborah Dressler; Nhat Nguyen; Kambiz Kaviani; Yueyong Wang (VLSID, 2014)

A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems. - Michael Bucher; Ravi T. Kollipara; Bruce Su; Liji Gopalakrishnan; Kashinath Prabhu; Pravin Kumar Venkatesan; Kambiz Kaviani; Barry Daly; William F. Stonecypher; Wayne D. Dettloff; Teva Stone; Fred Heaton; et al. (IEEE J. Solid State Circuits, 2014)

An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOS. - Ramin Farjadrad; Kambiz Kaviani; David Nguyen; Michael Brown; Govert Geelen; Corné Bastiaansen; Narendra Rao; Viswa Popuri; Greg Shen; Hamid Khatibi; Saudas Dey; Anirban Chatterjee; et al. (ISSCC, 2021)