Designing Moore FSM with Transformation of State Codes. - Kamil Mielcarek; Alexander Barkalov 001; Larisa Titarenko (CISIM, 2017)

Designing HFPGA-based Mealy FSMs with transformation of output functions. - Kamil Mielcarek; Alexander Barkalov 001; Larysa Titarenko (MIXDES, 2017)

Designing Moore FSM with extended class codes. - Kamil Mielcarek; Alexander Barkalov 001; Larysa Titarenko (MOCAST, 2017)

Twofold State Assignment for LUT-based Mealy FSMs. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek (MIXDES, 2018)

Design of FPGA-based Mealy FSMs with Counters. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek; Slawomir Chmielewski (MIXDES, 2018)

Encoding of Terms in LUT-based Mealy FSMs. - Alexander Barkalov 001; Larysa Titarenko; Malgorzata Mazurkiewicz; Kamil Mielcarek (MIXDES, 2018)

Twofold state assignment for FPGA-based mealy FSMs. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek (MOCAST, 2018)

Hardware Reduction for Lut-Based Mealy FSMs. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek (Int. J. Appl. Math. Comput. Sci., 2018)

Decreasing Number of LUTs for Moore FSMs. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek; Kazimierz Krzywicki; Wojciech Zajac (MIXDES, 2019)

Designing FPGA-Based Mealy FSMs with Two Levels of Logic. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek (MOCAST, 2019)

Encoding of Microoperations in FPGA-Based Moore FSMs. - Alexander Barkalov 001; Larysa Titarenko; Malgorzata Mazurkiewicz; Kamil Mielcarek (MOCAST, 2019)

Improving characteristics of LUT-based Mealy FSMs. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek (Int. J. Appl. Math. Comput. Sci., 2020)

Logic Synthesis for FPGA-Based Control Units - Structural Decomposition in Logic Design - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek; Slawomir Chmielewski (Springer, 2020)

Improving Characteristics of FSMs With Mixed Codes of Outputs. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski; Kamil Mielcarek (IEEE Access, 2022)

Reducing LUT Count for Mealy FSMs With Transformation of States. - Alexander A. Barkalov; Larysa Titarenko; Kamil Mielcarek (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Logic Synthesis for VLSI-Based Combined Finite State Machines - Synthesis Targeting ASICs, CPLDs and FPGAs - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek; Malgorzata Mazurkiewicz; Elzbieta Kawecka (Springer, 2022)

Hardware Reduction for FSMs With Extended State Codes. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek; Malgorzata Mazurkiewicz (IEEE Access, 2024)

Reducing the number of LUTs for Mealy FSMs with state transformation. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek (Int. J. Appl. Math. Comput. Sci., 2024)