Mixed-Mode Continuous-Time Video Acquisition Filters. - Kamran Azadet; J. Porte; F. Yang; J. E. D. Hurwitz (ISCAS, 1994)

The Design of CMOS Transconductor for High Frequency Continuous-Time Filter Applications. - F. Yang; PatrickSenn Loumeaeu; Kamran Azadet; Patrice Senn (ISCAS, 1994)

A Mismatch-Free CMOS Dynamic Voltage Comparator. - Kamran Azadet; Alex G. Dickinson; David A. Inglis (ISCAS, 1995)

A low-power 128-tap digital adaptive equalizer for broadband modems. - Chris J. Nicol; Patrik Larsson; Kamran Azadet; Jay H. O'Neill (IEEE J. Solid State Circuits, 1997)

Reconfigurable hardware for efficient implementation of programmable FIR filters. - Tracy C. Denk; Chris J. Nicol; Patrik Larsson; Kamran Azadet (ICASSP, 1998)

Low-power equalizer architectures for high-speed modems. - Kamran Azadet; Chris J. Nicole (IEEE Commun. Mag., 1998)

A 200-mW, 3.3-V, CMOS color camera IC producing 352×288 24-b video at 30 frames/s. - Marc J. Loinaz; Kanwar Jit Singh; Andrew J. Blanksby; David A. Inglis; Kamran Azadet; Bryan D. Ackland (IEEE J. Solid State Circuits, 1998)

A low complexity joint equalizer and decoder for 1000Base-T Gigabit Ethernet. - Erich F. Haratsch; Kamran Azadet (CICC, 2000)

Pipelined reduced-state sequence estimation. - Erich F. Haratsch; Kamran Azadet (GLOBECOM, 2000)

Reduced-State Sequence Estimation with Tap-Selectable Decision-Feedback. - Erich F. Haratsch; Andrew J. Blanksby; Kamran Azadet (ICC (1), 2000)

High-speed reduced-state sequence estimation. - Erich F. Haratsch; Kamran Azadet (ISCAS, 2000)

DSP techniques for optical transceivers. - Kamran Azadet; Erich Haratsch; Helen Kim; Fadi Saibi; Jeffrey H. Saunders; Mike Shaffer; Leilei Song; Meng-Lin Yu (CICC, 2001)

A 1-Gb/s joint equalizer and trellis decoder for 1000BASE-T Gigabit Ethernet. - Erich F. Haratsch; Kamran Azadet (IEEE J. Solid State Circuits, 2001)

A low power adaptive filter using dynamic reduced 2's-complement representation. - Zhan Yu; Meng-Lin Yu; Kamran Azadet; Alan N. Willson Jr. (CICC, 2002)

The use of reduced two's-complement representation in low-power DSP design. - Zhan Yu; Meng-Lin Yu; Kamran Azadet; Alan N. Willson Jr. (ISCAS (1), 2002)

Equalization and FEC techniques for optical transceivers. - Kamran Azadet; Erich F. Haratsch; Helen Kim; Fadi Saibi; Jeffrey H. Saunders; Michael Shaffer; Leilei Song; Meng-Lin Yu (IEEE J. Solid State Circuits, 2002)

Frequency-interleaving technique for high-speed A/D conversion. - Guillaume Ding; Catherine Dehollain; Michel J. Declercq; Kamran Azadet (ISCAS (1), 2003)

An integrated CMOS transceiver for a 40Gb/s SCM optical communication system. - Jinghong Chen; Fadi Saibi; Eduard Säckinger; Kamran Azadet; Joe Othmer; Mark Yu; Fuji Yang; Jenshan Lin; Titus Huang; Tingping Liu (CICC, 2005)

A Multi-Carrier QAM Transceiver for Ultra-Wideband Optical Communication. - Jinghong Chen; Fadi Saibi; Eduard Säckinger; Joseph H. Othmer; Meng-Lin (Mark) Yu; Fuji Yang; Jenshan Lin; Titus Huang; Tingping Liu; Kamran Azadet (IEEE J. Solid State Circuits, 2006)

Toward Maximizing Throughput in Wireless Relay: A General User Cooperation Model. - Meng Yu 002; Jing (Tiffany) Li; Rick S. Blum; Kamran Azadet (CISS, 2007)

A power-optimized reconfigurable CT ΔΣ modulator in 65nm CMOS. - Rui Wang 035; Xiaoke Wen; Kamran Azadet; Changzhi Li; Jinghong Chen (ISCAS, 2012)

A 150 MHz bandwidth continuous-time ΔΣ modulator in 28 nm CMOS with DAC calibration. - Rui Wang 035; Yang You; Guoying Wu; Xiaoke Wen; Tianshi He; Jinghong Chen; Kamran Azadet; Ping Gui (MWSCAS, 2015)

Nonlinearity Modeling of a Chireix Outphasing Power Amplifier. - Taesong Hwang; Kamran Azadet; Ross S. Wilson; Jenshan Lin (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

10.7 A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D Converters. - Martin Clara; Daniel Gruber; Albert Molina; Matteo Camponeschi; Yu-shan Wang; Christian Lindholm; Hundo Shin; Ramón Sanchez-Perez; Christoph Duller; Patrick Torta; Kamran Azadet (ISSCC, 2021)

10.6 A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET. - Daniel Gruber; Martin Clara; Ramón Sanchez-Perez; Yu-shan Wang; Christoph Duller; Gerald Rauter; Patrick Torta; Kamran Azadet (ISSCC, 2021)

A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS. - Edwin Thaller; Run Levinger; Evgeny Shumaker; Aryeh Farber; Sergey Bershansky; Nir Geron; Ashoke Ravi; Rotem Banin; Jasmin Kadry; Gil Horovitz; Christian Krassnitzer; Christoph Duller; et al. (ISSCC, 2021)

A 12-b 16-GS/s RF-Sampling Capacitive DAC for Multi-Band Soft Radio Base-Station Applications With On-Chip Transmission-Line Matching Network in 16-nm FinFET. - Daniel Gruber; Martin Clara; Ramón Sanchez-Perez; Yu-shan Wang; Christoph Duller; Gerald Rauter; Patrick Torta; Gerhard Knoblinger; Kamran Azadet (IEEE J. Solid State Circuits, 2021)