A power-efficient architecture for high-speed D/A converters. - Kamran Farzan; David A. Johns (ISCAS (1), 2003)

A low-complexity power-efficient signaling scheme for chip-to-chip communication. - Kamran Farzan; David A. Johns (ISCAS (5), 2003)

A power-efficient 4-PAM signaling scheme with convolutional encoder in space for chip-to-chip communication. - Kamran Farzan; David A. Johns (ESSCIRC, 2004)

A low-power crosstalk-insensitive signaling scheme for chip-to-chip communication. - Kamran Farzan; David A. Johns (ISCAS (4), 2004)

A CMOS 10-gb/s power-efficient 4-PAM transmitter. - Kamran Farzan; David A. Johns (IEEE J. Solid State Circuits, 2004)

Coding schemes for chip-to-chip interconnect applications. - Kamran Farzan; David A. Johns (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A Robust 4-PAM Signaling Scheme for Inter-Chip Links Using Coding in Space. - Kamran Farzan; David A. Johns (IEEE Trans. Very Large Scale Integr. Syst., 2008)

A low jitter 2.7mW/Gbps 180Gb/s 12-lane transmitter in a 40nm CMOS technology. - Kamran Farzan; Mehrdad Ramezani; Angus McLaren; Roman Pahuta; Nadeesha Amarasinghe; David Cassan; Saman Sadr (ESSCIRC, 2012)

A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support. - Mohammad Sadegh Jalali; Mohammad Hossein Taghavi; Angus McLaren; Jennifer Pham; Kamran Farzan; Dominic DiClemente; Marcus van Ierssel; William Song; Saman Asgaran; Chris D. Holdenried; Saman Sadr (ISSCC, 2018)

11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS. - Ravi Shivnaraine; Marcus van Ierssel; Kamran Farzan; Dominic DiClemente; George Ng; Nanyan Wang; Javid Musayev; Gairik Dutta; Masumi Shibata; Arash Moradi; Haleh Vahedi; Manavi Farzad; et al. (ISSCC, 2021)