The Influence Factors and Mechanism of Societal Risk Perception. - Rui Zheng; Kan Shi; Shu Li 001 (Complex (2), 2009)

Accuracy-Performance Tradeoffs on an FPGA through Overclocking. - Kan Shi; David Boland; George A. Constantinides (FCCM, 2013)

Overclocking datapath for latency-error tradeoff. - Kan Shi; David Boland; George A. Constantinides (ISCAS, 2013)

Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs. - Kan Shi; David Boland; Edward A. Stott; Samuel Bayliss; George A. Constantinides (DAC, 2014)

Efficient FPGA implementation of digit parallel online arithmetic operators. - Kan Shi; David Boland; George A. Constantinides (FPT, 2014)

Combining grey systems theory and entropy method to evaluate the organizational health. - Xiaoqian Liu; Kan Shi; Lei Xing (FSKD, 2014)

Delay Test for Diagnosis of Power Switches. - S. Saqib Khursheed; Kan Shi; Bashir M. Al-Hashimi; Peter R. Wilson; Krishnendu Chakrabarty (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Imprecise Datapath Design: An Overclocking Approach. - Kan Shi; David Boland; George A. Constantinides (ACM Trans. Reconfigurable Technol. Syst., 2015)

Increasing Flexibility of Cloud FPGA Virtualization. - Jinjie Ruan; Yisong Chang; Ke Zhang 017; Kan Shi; Mingyu Chen 001; Yungang Bao (FPL, 2022)

Towards Developing High Performance RISC-V Processors Using Agile Methodology. - Yinan Xu 001; Zihao Yu; Dan Tang; Guokai Chen; Lu Chen; Lingrui Gou; Yue Jin; Qianruo Li; Xin Li; Zuojun Li; Jiawei Lin; Tong Liu; et al. (MICRO, 2022)

ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration. - Kan Shi; Shuoxiang Xu; Yuhan Diao; David Boland; Yungang Bao (FPGA, 2023)

Functional Verification for Agile Processor Development: A Case for Workflow Integration. - Yinan Xu 001; Zihao Yu; Kaifan Wang; Huaqiang Wang; Jiawei Lin; Yue Jin; Linjuan Zhang; Zifei Zhang 001; Dan Tang; Sa Wang; Kan Shi; Ninghui Sun; et al. (J. Comput. Sci. Technol., 2023)

Hassert: Hardware Assertion-Based Verification Framework with FPGA Acceleration. - Ziqing Zhang; Weijie Weng; Yaning Li; Lijia Cai; Haoyu Wang; David Boland; Yungang Bao; Kan Shi (ASPLOS (4), 2024)

Corvus: Efficient HW/SW Co-Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration. - Zijian Jiang; Keran Zheng; David Boland; Yungang Bao; Kan Shi (ASP-DAC, 2025)

Latency Insensitivity Testing for Dataflow HLS Designs. - Jianyi Cheng; Lianghui Wang; Zijian Jiang; Yungang Bao; Kan Shi (FPGA, 2025)

Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration. - Shuoxiang Xu; Zijian Jiang; Yuxin Zhang; David Boland; Yungang Bao; Kan Shi (FPGA, 2025)

Poby: SmartNIC-accelerated Image Provisioning for Coldstart in Clouds. - Zihao Chang; Jiaqi Zhu; Haifeng Sun 004; Yunlong Xie; Kan Shi; Ninghui Sun; Yungang Bao; Sa Wang (USENIX ATC, 2025)