A novel test-data compression technique using application-aware bitmask and dictionary selection methods. - Kanad Basu; Prabhat Mishra 001 (ACM Great Lakes Symposium on VLSI, 2008)

Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods. - Kanad Basu; Prabhat Mishra 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Efficient combination of trace and scan signals for post silicon validation and debug. - Kanad Basu; Prabhat Mishra 001; Priyadarsan Patra (ITC, 2011)

Efficient Trace Signal Selection for Post Silicon Validation and Debug. - Kanad Basu; Prabhat Mishra 001 (VLSI Design, 2011)

Efficient trace data compression using statically selected dictionary. - Kanad Basu; Prabhat Mishra 001 (VTS, 2011)

Constrained signal selection for post-silicon validation. - Kanad Basu; Prabhat Mishra 001; Priyadarsan Patra (HLDVT, 2012)

A Novel Approach for Handling Misbehaving Nodes in Behavior-Aware Mobile Networking - Kanad Basu; Subrata Mitra; Srishti Mukherjee; Weixun Wang (CoRR, 2012)

Dynamic Selection of Trace Signals for Post-Silicon Debug. - Kanad Basu; Prabhat Mishra 001; Priyadarsan Patra; Amir Nahir; Allon Adir (MTV, 2013)

Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults. - Kanad Basu; Prabhat Mishra 001; Priyadarsan Patra (VLSI Design, 2013)

Bitmask aware compression of NISC control words. - Kanad Basu; Chetan Murthy; Prabhat Mishra 001 (Integr., 2013)

RATS: Restoration-Aware Trace Signal Selection for Post-Silicon Validation. - Kanad Basu; Prabhat Mishra 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Post-Silicon Validation and Diagnosis. - Kanad Basu; Subhadip Kundu (VLSID, 2016)

RTL level trace signal selection and coverage estimation during post-silicon validation. - Binod Kumar 001; Kanad Basu; Masahiro Fujita; Virendra Singh (HLDVT, 2017)

A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection. - Binod Kumar 001; Kanad Basu; Ankit Jindal; Brajesh Pandey; Masahiro Fujita (VDAT, 2017)

Deterministic Shift Power Reduction in Test Compression. - Kanad Basu; Rishi Kumar; Santosh Kulkarni 002; Rohit Kapur (VDAT, 2017)

Improving post-silicon error detection with topological selection of trace signals. - Binod Kumar 001; Kanad Basu; Ankit Jindal; Masahiro Fujita; Virendra Singh (VLSI-SoC, 2017)

A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging. - Binod Kumar 001; Kanad Basu; Virendra Singh (IGSC, 2018)

Abetting Planned Obsolescence by Aging 3D Networks-on-Chip. - Sourav Das 002; Kanad Basu; Janardhan Rao Doppa; Partha Pratim Pande; Ramesh Karri; Krishnendu Chakrabarty (NOCS, 2018)

ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis. - Ankit Jindal; Binod Kumar 001; Kanad Basu; Masahiro Fujita (VLSID, 2018)

Special session on intelligent sensor nodes. - Kanad Basu; Shreyas Sen (VTS, 2018)

Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator. - Jeff Jun Zhang; Tianyu Gu; Kanad Basu; Siddharth Garg (VTS, 2018)

Can Monitoring System State + Counting Custom Instruction Sequences Aid Malware Detection? - Aditya Rohan; Kanad Basu; Ramesh Karri (ATS, 2019)

PREEMPT: PReempting Malware by Examining Embedded Processor Traces. - Kanad Basu; Rana Elnaggar; Krishnendu Chakrabarty; Ramesh Karri (DAC, 2019)

High-Level Synthesis of Benevolent Trojans. - Christian Pilato; Kanad Basu; Mohammed Shayan; Francesco Regazzoni 001; Ramesh Karri (DATE, 2019)

Power, Area, Speed, and Security (PASS) Trade-Offs of NIST PQC Signature Candidates Using a C to ASIC Design Flow. - Deepraj Soni; Mohammed Nabeel 001; Kanad Basu; Ramesh Karri (ICCD, 2019)

Efficient Post-Silicon Validation of Network-on-Chip Using Wireless Links. - Sidhartha Sankar Rout; Kanad Basu; Sujay Deb (VLSID, 2019)

Hardware Trojans Inspired IP Watermarks. - Mohammed Shayan; Kanad Basu; Ramesh Karri (IEEE Des. Test, 2019)

Fault-Tolerant Systolic Array Based Accelerators for Deep Neural Network Execution. - Jeff Jun Zhang; Kanad Basu; Siddharth Garg (IEEE Des. Test, 2019)

Guest Editorial. - Kanad Basu; Mingsong Chen 001; Rubin A. Parekhji (J. Electron. Test., 2019)

NIST Post-Quantum Cryptography- A Hardware Evaluation Study. - Kanad Basu; Deepraj Soni; Mohammed Nabeel 001; Ramesh Karri (IACR Cryptol. ePrint Arch., 2019)

CAD-Base: An Attack Vector into the Electronics Supply Chain. - Kanad Basu; Samah Mohamed Saeed; Christian Pilato; Mohammed Ashraf; Mohammed Thari Nabeel; Krishnendu Chakrabarty; Ramesh Karri (ACM Trans. Design Autom. Electr. Syst., 2019)

Black-Hat High-Level Synthesis: Myth or Reality? - Christian Pilato; Kanad Basu; Francesco Regazzoni 001; Ramesh Karri (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Defense Against on-Chip Trojans Enabling Traffic Analysis Attacks. - M. Meraj Ahmed; Abhijitt Dhavlle; Naseef Mansoor; Purab Ranjan Sutradhar; Sai Manoj Pudukotai Dinakarrao; Kanad Basu; Amlan Ganguly (AsianHOST, 2020)

ND-HMDs: Non-Differentiable Hardware Malware Detectors against Evasive Transient Execution Attacks. - Md. Shohidul Islam; Abraham Peedikayil Kuruvila; Kanad Basu; Khaled N. Khasawneh (ICCD, 2020)

High-level Modeling of Manufacturing Faults in Deep Neural Network Accelerators. - Shamik Kundu; Ahmet Soyyigit; Khaza Anuarul Hoque; Kanad Basu (IOLTS, 2020)

Analyzing the Efficiency of Machine Learning Classifiers in Hardware-Based Malware Detectors. - Abraham Peedikayil Kuruvila; Shamik Kundu; Kanad Basu (ISVLSI, 2020)

A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors. - Binod Kumar 001; Swapniel Thakur; Kanad Basu; Masahiro Fujita; Virendra Singh (VLSID, 2020)

Special Session: The Recent Advance in Hardware Implementation of Post-Quantum Cryptography. - Jiafeng Xie; Kanad Basu; Kris Gaj; Ujjwal Guin (VTS, 2020)

Hardware Trojan Detection Using Controlled Circuit Aging. - Virinchi Roy Surabhi; Prashanth Krishnamurthy; Hussam Amrouch; Kanad Basu; Jörg Henkel; Ramesh Karri; Farshad Khorrami (IEEE Access, 2020)

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. - Benjamin Tan 001; Ramesh Karri; Nimisha Limaye; Abhrajit Sengupta; Ozgur Sinanoglu; Md. Moshiur Rahman 001; Swarup Bhunia; Danielle Duvalsaint; Ronald D. Blanton; Amin Rezaei 001; Yuanqi Shen; Hai Zhou 001; et al. (CoRR, 2020)

Hardware-Assisted Detection of Firmware Attacks in Inverter-Based Cyberphysical Microgrids. - Abraham Peedikayil Kuruvila; Ioannis Zografopoulos; Kanad Basu; Charalambos Konstantinou (CoRR, 2020)

Security Assessment of Interposer-based Chiplet Integration. - Mohammed Shayan; Kanad Basu; Ramesh Karri (CoRR, 2020)

Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection. - Binod Kumar 001; Kanad Basu; Masahiro Fujita; Virendra Singh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

COPPTCHA: COPPA Tracking by Checking Hardware-Level Activity. - Kanad Basu; Suha Sabi Hussain; Ujjwal Gupta; Ramesh Karri (IEEE Trans. Inf. Forensics Secur., 2020)

A Theoretical Study of Hardware Performance Counters-Based Malware Detection. - Kanad Basu; Prashanth Krishnamurthy; Farshad Khorrami; Ramesh Karri (IEEE Trans. Inf. Forensics Secur., 2020)

A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug. - Binod Kumar 001; Jay Adhaduk; Kanad Basu; Masahiro Fujita; Virendra Singh (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Secure Logic Locking with Strain-Protected Nanomagnet Logic. - Naimul Hassan; Alexander J. Edwards; Dhritiman Bhattacharya; Mustafa M. Shihab; Varun Venkat; Peng Zhou; Xuan Hu 002; Shamik Kundu; Abraham Peedikayil Kuruvila; Kanad Basu; Jayasimha Atulasimha; Yiorgos Makris; et al. (DAC, 2021)

Hardware-assisted Detection of Malware in Automotive-Based Systems. - Yugpratap Singh; Abraham Peedikayil Kuruvila; Kanad Basu (DATE, 2021)

Time Series-Based Malware Detection Using Hardware Performance Counters. - Abraham Peedikayil Kuruvila; Sayar Karmakar; Kanad Basu (HOST, 2021)

An Ultra-efficient Look-up Table based Programmable Processing in Memory Architecture for Data Encryption. - Purab Ranjan Sutradhar; Kanad Basu; Sai Manoj Pudukotai Dinakarrao; Amlan Ganguly (ICCD, 2021)

What Can a Remote Access Hardware Trojan do to a Network-on-Chip? - M. Meraj Ahmed; Abhijitt Dhavlle; Naseef Mansoor; Sai Manoj Pudukotai Dinakarrao; Kanad Basu; Amlan Ganguly (ISCAS, 2021)

Can Overclocking Detect Hardware Trojans? - Xingyu Meng; Rakibul Hassan; Sai Manoj Pudukotai Dinakarrao; Kanad Basu (ISCAS, 2021)

HardCompress: A Novel Hardware-based Low-power Compression Scheme for DNN Accelerators. - Ayush Arunachalam; Shamik Kundu; Arnab Raha; Suvadeep Banerjee; Suriyaprakash Natarajan; Kanad Basu (ISQED, 2021)

Application of Machine Learning in Hardware Trojan Detection. - Shamik Kundu; Xingyu Meng; Kanad Basu (ISQED, 2021)

Exploring Fault-Energy Trade-offs in Approximate DNN Hardware Accelerators. - Ayesha Siddique; Kanad Basu; Khaza Anuarul Hoque (ISQED, 2021)

Efficient Hierarchical Post-Silicon Validation and Debug. - Pandy Kalimuthu; Kanad Basu; Benjamin Carrión Schäfer (VLSID, 2021)

Special Session: Reliability Analysis for AI/ML Hardware. - Shamik Kundu; Kanad Basu; Mehdi Sadi; Twisha Titirsha; Shihao Song; Anup Das 001; Ujjwal Guin (VTS, 2021)

Special Session: Reliability Analysis for ML/AI Hardware. - Shamik Kundu; Kanad Basu; Mehdi Sadi; Twisha Titirsha; Shihao Song; Anup Das 001; Ujjwal Guin (CoRR, 2021)

Hardware Security in Emerging Technologies: Vulnerabilities, Attacks, and Solutions. - Naghmeh Karimi; Kanad Basu; Chip-Hong Chang; Jason M. Fung (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security. - Wenye Liu; Chip-Hong Chang; Xueyang Wang; Chen Liu 013; Jason M. Fung; Mohammad Ebrahimabadi; Naghmeh Karimi; Xingyu Meng; Kanad Basu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

SoCCAR: Detecting System-on-Chip Security Violations Under Asynchronous Resets. - Xingyu Meng; Kshitij Raj; Atul Prasad Deb Nath; Kanad Basu; Sandip Ray (IACR Cryptol. ePrint Arch., 2021)

Defending Hardware-Based Malware Detectors Against Adversarial Attacks. - Abraham Peedikayil Kuruvila; Shamik Kundu; Kanad Basu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

WiND: An Efficient Post-Silicon Debug Strategy for Network on Chip. - Sidhartha Sankar Rout; Sujay Deb; Kanad Basu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Hardware Performance Counters: Ready-Made vs Tailor-Made. - Abraham Peedikayil Kuruvila; Anushree Mahapatra; Ramesh Karri; Kanad Basu (ACM Trans. Embed. Comput. Syst., 2021)

Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators. - Shamik Kundu; Suvadeep Banerjee; Arnab Raha; Suriyaprakash Natarajan; Kanad Basu (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A Semi-formal Information Flow Validation for Analyzing Secret Asset Propagation in COTS IC Integrated Systems. - Xingyu Meng; Mahmudul Hasan 012; Kanad Basu; Tamzidul Hoque (ACM Great Lakes Symposium on VLSI, 2022)

Design and Analysis of a Scalable and Efficient Quantum Circuit for LWE Matrix Arithmetic. - Chao Lu; Utsav Banerjee; Kanad Basu (ICCD, 2022)

Detecting Functional Safety Violations in Online AI Accelerators. - Shamik Kundu; Kanad Basu (IOLTS, 2022)

Design and Logic Synthesis of a Scalable, Efficient Quantum Number Theoretic Transform. - Chao Lu; Shamik Kundu; Abraham Peedikayil Kuruvila; Supriya Margabandhu Ravichandran; Kanad Basu (ISLPED, 2022)

Fault Resilience of DNN Accelerators for Compressed Sensor Inputs. - Ayush Arunachalam; Shamik Kundu; Arnab Raha; Suvadeep Banerjee; Kanad Basu (ISVLSI, 2022)

Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs. - Ayush Arunachalam; Athulya Kizhakkayil; Shamik Kundu; Arnab Raha; Suvadeep Banerjee; Robert Jin; Fei Su; Kanad Basu (ITC, 2022)

RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators. - Shamik Kundu; Akul Malhotra; Arnab Raha; Sumeet Kumar Gupta; Kanad Basu (ITC, 2022)

Special Session: Effective In-field Testing of Deep Neural Network Hardware Accelerators. - Shamik Kundu; Suvadeep Banerjee; Arnab Raha; Kanad Basu (VTS, 2022)

Machine Learning-enhanced Efficient Spectroscopic Ellipsometry Modeling. - Ayush Arunachalam; S. Novia Berriel; Parag Banerjee; Kanad Basu (CoRR, 2022)

A Security Analysis of Circuit Clock Obfuscation. - Rajesh Datta; Guangwei Zhao; Kanad Basu; Kaveh Shamsi (Cryptogr., 2022)

Runtime Malware Detection Using Embedded Trace Buffers. - Rana Elnaggar; Kanad Basu; Krishnendu Chakrabarty; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Explainable Machine Learning for Intrusion Detection via Hardware Performance Counters. - Abraham Peedikayil Kuruvila; Xingyu Meng; Shamik Kundu; Gaurav Pandey 004; Kanad Basu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

RTL-ConTest: Concolic Testing on RTL for Detecting Security Vulnerabilities. - Xingyu Meng; Shamik Kundu; Arun K. Kanuparthi; Kanad Basu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Real-Time Hardware-Based Malware and Micro-Architectural Attack Detection Utilizing CMOS Reservoir Computing. - Sanjeev Tannirkulam Chandrasekaran; Abraham Peedikayil Kuruvila; Kanad Basu; Arindam Sanyal (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

PolyWorm: Leveraging Polymorphic Behavior to Implant Hardware Trojans. - Nimisha Limaye; Nikhil Rangarajan; Satwik Patnaik; Ozgur Sinanoglu; Kanad Basu (IEEE Trans. Emerg. Top. Comput., 2022)

Towards High-Level Synthesis of Quantum Circuits. - Chao Lu; Christian Pilato; Kanad Basu (DATE, 2023)

Search Space Reduction for Efficient Quantum Compilation. - Amisha Srivastava; Chao Lu; Navnil Choudhury; Ayush Arunachalam; Kanad Basu (ACM Great Lakes Symposium on VLSI, 2023)

Application Profiling Using Register-Instruction Hardware Performance Counters. - Anand Menon; Amisha Srivastava; Shamik Kundu; Kanad Basu (ISVLSI, 2023)

Enhanced ML-Based Approach for Functional Safety Improvement in Automotive AMS Circuits. - Ayush Arunachalam; Sanjay Das; Monikka Rajan; Fei Su; Xiankun Jin; Suvadeep Banerjee; Arnab Raha; Suriyaprakash Natarajan; Kanad Basu (ITC, 2023)

Bottlenecks in Secure Adoption of Deep Neural Networks in Safety-Critical Applications. - Sanjay Das; Shamik Kundu; Kanad Basu (MWSCAS, 2023)

Unlocking Hardware Security Assurance: The Potential of LLMs. - Xingyu Meng; Amisha Srivastava; Ayush Arunachalam; Avik Ray; Pedro Henrique Silva; Rafail Psiakis; Yiorgos Makris; Kanad Basu (CoRR, 2023)

A Needle in the Haystack: Inspecting Circuit Layout to Identify Hardware Trojans. - Xingyu Meng; Abhrajit Sengupta; Kanad Basu (IACR Cryptol. ePrint Arch., 2023)

SeVNoC: Security Validation of System-on-Chip Designs With NoC Fabrics. - Xingyu Meng; Kshitij Raj; Sandip Ray; Kanad Basu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Analysis and Mitigation of DRAM Faults in Sparse-DNN Accelerators. - Shamik Kundu; Arnab Raha; Suvadeep Banerjee; Suriyaprakash Natarajan; Kanad Basu (IEEE Des. Test, 2023)

A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning Accelerators. - Ayush Arunachalam; Shamik Kundu; Arnab Raha; Suvadeep Banerjee; Suriyaprakash Natarajan; Kanad Basu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

SeqL+: Secure Scan-Obfuscation With Theoretical and Empirical Validation. - Seetal Potluri; Shamik Kundu; Akash Kumar 001; Kanad Basu; Aydin Aysu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Trouble-Shooting at GAN Point: Improving Functional Safety in Deep Learning Accelerators. - Shamik Kundu; Suvadeep Banerjee; Arnab Raha; Fei Su; Suriyaprakash Natarajan; Kanad Basu (IEEE Trans. Computers, 2023)

Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection. - Rakibul Hassan; Xingyu Meng; Kanad Basu; Sai Manoj Pudukotai Dinakarrao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Defense Against On-Chip Trojans Enabling Traffic Analysis Attacks Based on Machine Learning and Data Augmentation. - Abhijitt Dhavlle; M. Meraj Ahmed; Naseef Mansoor; Kanad Basu; Amlan Ganguly; Sai Manoj Pudukotai Dinakarrao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Graph Learning-based Fault Criticality Analysis for Enhancing Functional Safety of E/E Systems. - Sanjay Das; Shamik Kundu; Pooja Madhusoodhanan; Viswanathan Pillai Prasanth; Rubin A. Parekhji; Arnab Raha; Suvadeep Banerjee; Suriya Natarajan; Kanad Basu (DAC, 2024)

MENDNet: Just-in-time Fault Detection and Mitigation in AI Systems with Uncertainty Quantification and Multi-Exit Networks. - Shamik Kundu; Mirazul Haque; Sanjay Das; Wei Yang 013; Kanad Basu (DAC, 2024)

NSPG: Natural language Processing-based Security Property Generator for Hardware Security Assurance. - Xingyu Meng; Amisha Srivastava; Ayush Arunachalam; Avik Ray; Pedro Henrique Silva; Rafail Psiakis; Yiorgos Makris; Kanad Basu (DAC, 2024)

Assert-O: Context-based Assertion Optimization using LLMs. - Samit Shahnawaz Miftah; Amisha Srivastava; Hyunmin Kim; Kanad Basu (ACM Great Lakes Symposium on VLSI, 2024)

Explainability to the Rescue: A Pattern-Based Approach for Detecting Adversarial Attacks. - Sanjay Das; Shamik Kundu; Kanad Basu (HOST, 2024)

QNAD: Quantum Noise Injection for Adversarial Defense in Deep Neural Networks. - Shamik Kundu; Navnil Choudhury; Sanjay Das; Arnab Raha; Kanad Basu (HOST, 2024)

RTL-Spec: RTL Spectrum Analysis for Security Bug Localization. - Samit Shahnawaz Miftah; Shamik Kundu; Austin Mordahl; Shiyi Wei; Kanad Basu (HOST, 2024)

QuEST: Quantum Circuit Output Estimation using Gaussian Distribution Analysis. - Shamik Kundu; Navnil Choudhury; Kanad Basu (ISQED, 2024)

RASH: Reliable Deep Learning Acceleration using Sparsity-based Hardware. - Shamik Kundu; Arnab Raha; Deepak A. Mathaikutty; Kanad Basu (ISQED, 2024)

A Survey of Side-Channel Attacks in Superconducting Quantum Computers. - Navnil Choudhury; Kanad Basu (ISVLSI, 2024)

Machine Learning Intervened RIS-Based RF Interference Management for IoT. - Sakib Reza; Sanjay Das; Shamik Kundu; Kanad Basu; Ifana Mahbub (ISVLSI, 2024)

PristiQ: A Co-Design Framework for Preserving Data Security of Quantum Learning in the Cloud. - Zhepeng Wang 001; Yi Sheng; Nirajan Koirala; Kanad Basu; Taeho Jung; Cheng-Chang Lu; Weiwen Jiang (ISVLSI, 2024)

QuaSi: A Scalable and Reliable Quantum Simulation-based Equivalence Checking Framework. - Chao Lu; Navnil Choudhury; Kanad Basu (QCE, 2024)

Hardware-based Detection of Malicious Firmware Modification in Microgrids. - Amisha Srivastava; Sneha Thakur; Abraham Peedikayil Kuruvila; Poras T. Balsara; Kanad Basu (VLSID, 2024)

Analyzing and Mitigating Circuit Aging Effects in Deep Learning Accelerators. - Sanjay Das; Shamik Kundu; Anand Menon; Yihui Ren 001; Shubha R. Kharel; Kanad Basu (VTS, 2024)

Quantum Assertion Scheme for Assuring Qudit Robustness. - Navnil Choudhury; Chao Lu; Kanad Basu (IEEE Comput. Archit. Lett., 2024)

Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning. - Ayush Arunachalam; Ian Kintz; Suvadeep Banerjee; Arnab Raha; Xiankun Jin; Fei Su; Viswanathan Pillai Prasanth; Rubin A. Parekhji; Suriyaprakash Natarajan; Kanad Basu (CoRR, 2024)

AttentionBreaker: Adaptive Evolutionary Optimization for Unmasking Vulnerabilities in LLMs through Bit-Flip Attacks. - Sanjay Das; Swastik Bhattacharya; Souvik Kundu 009; Shamik Kundu; Anand Menon; Arnab Raha; Kanad Basu (CoRR, 2024)

Bit-by-Bit: Investigating the Vulnerabilities of Binary Neural Networks to Adversarial Bit Flipping. - Shamik Kundu; Sanjay Das; Sayar Karmakar; Arnab Raha; Souvik Kundu 009; Yiorgos Makris; Kanad Basu (Trans. Mach. Learn. Res., 2024)

DiagNNose: Toward Error Localization in Deep Learning Hardware-Based on VTA-TVM Stack. - Shamik Kundu; Suvadeep Banerjee; Arnab Raha; Suriyaprakash Natarajan; Kanad Basu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

SCAR: Power Side-Channel Analysis at RTL Level. - Amisha Srivastava; Sanjay Das; Navnil Choudhury; Rafail Psiakis; Pedro Henrique Silva; Debjit Pal; Kanad Basu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

QuBEC: Boosting Equivalence Checking for Quantum Circuits With QEC Embedding. - Chao Lu; Navnil Choudhury; Utsav Banerjee; Abdullah Ash-Saki; Kanad Basu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

System-on-Chip Information Flow Validation Under Asynchronous Resets. - Samit Shahnawaz Miftah; Kshitij Raj; Xingyu Meng; Sandip Ray; Kanad Basu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

QHLS: An HLS Framework to Convert High-Level Descriptions to Quantum Circuits. - Chao Lu; Christian Pilato; Kanad Basu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

CONCEAL: Covert NoC Exploitation in In-Memory Computing-based DNN Accelerators. - Sanjay Das; Shamik Kundu; Sumit Kumar Mandal; Kanad Basu (COINS, 2025)

Enhancing AMS Circuit Reliability: An Anomaly Dataset for Functional Safety Research in Automotive SoCs. - Sanjay Das; Anand Menon; Omar Abiola Abioye; Afreen Fatimah Khazi-Syed; Jonathan Edward Lee; Ayush Arunachalam; Shamik Kundu; Pooja Madhusoodhanan; Prasanth Viswanathan Pillai; Rubin A. Parekhji; Arnab Raha; Suvadeep Banerjee; et al. (ACM Great Lakes Symposium on VLSI, 2025)

Quantum Leak: Timing Side-Channel Attacks on Cloud-Based Quantum Services. - Chao Lu; Esha Telang; Aydin Aysu; Kanad Basu (ACM Great Lakes Symposium on VLSI, 2025)

Crosstalk-induced Side Channel Threats in Multi-Tenant NISQ Computers. - Navnil Choudhury; Chaithanya Naik Mude; Sanjay Das; Preetham Chandra Tikkireddi; Swamit Tannu; Kanad Basu (NDSS, 2025)

Efficient Explainable Boosting Machine for RF Active Metasurface Array Synthesis. - Sakib Reza; Sanjay Das; Shamik Kundu; Kanad Basu; Ifana Mahbub (RWS, 2025)

Advancing Functional Safety: Improving Failure Mode Analysis and Fault Injection Using Automation and GNN Algorithms. - Amurt Prakash; Abhijeet Singh; Pooja Madhusoodhanan; Padma Arvind; Viswanathan Pillai Prasanth; Sanjay Das; Kanad Basu (VLSID, 2025)

OpenAssert: Towards Secure Assertion Generation using Large Language Models. - Anand Menon; Samit Shahnawaz Miftah; Amisha Srivastava; Shamik Kundu; Shovik Kundu; Arnab Raha; Suvadeep Banerjee; Deepak Mathaikutty; Kanad Basu (VTS, 2025)

Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Dataset. - Anand Menon; Samit S. Miftah; Shamik Kundu; Souvik Kundu 009; Amisha Srivastava; Arnab Raha; Gabriel Theodor Sonnenschein; Suvadeep Banerjee; Deepak Mathaikutty; Kanad Basu (CoRR, 2025)

QubitHammer Attacks: Qubit Flipping Attacks in Multi-tenant Superconducting Quantum Computers. - Yizhuo Tan; Navnil Choudhury; Kanad Basu; Jakub Szefer (CoRR, 2025)

Hardware-Enabled Mechanisms for Verifying Responsible AI Development. - Aidan O'Gara; Gabriel Kulp; Will Hodgkins; James Petrie; Vincent Immler; Aydin Aysu; Kanad Basu; Shivam Bhasin; Stjepan Picek; Ankur Srivastava 001 (CoRR, 2025)

PoSyn: Secure Power Side-Channel Aware Synthesis. - Amisha Srivastava; Samit Shahnawaz Miftah; Hyunmin Kim; Debjit Pal; Kanad Basu (CoRR, 2025)