Dynamic Allocation of Physical Register Banks for an SMT Processor. - Norito Kato; Masanori Yamato; Osamu Tujimoto; Mikiko Sato; Koichi Sasada; Kaname Uchikura; Mitaro Namiki; Hironori Nakajo (PDPTA, 2004)

A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. - Yoshiyasu Ogasawara; Norito Kato; Masanori Yamato; Mikiko Sato; Koichi Sasada; Kaname Uchikura; Mitaro Namiki; Hironori Nakajo (PDPTA, 2005)

Development of a Thread Scheduler for SMT Processor Architecture. - Kaname Uchikura; Koichi Sasada; Mikiko Sato; Masanori Yamato; Norito Kato; Hironori Nakajo; Mitaro Namiki (PDPTA, 2005)

Towards Reconfigurable Cache Memory for a Multithreaded Processor. - Yoshiyasu Ogasawara; Ippei Tate; Satoshi Watanabe; Mikiko Sato; Koichi Sasada; Kaname Uchikura; Kazunari Asano; Mitaro Namiki; Hironori Nakajo (PDPTA, 2006)

A Model of Implementable SMT Processor on FPGA. - Ippei Tate; Yoshiyasu Ogasawara; Mikiko Sato; Koichi Sasada; Kaname Uchikura; Kazunari Asano; Satoshi Watanabe; Mitaro Namiki; Hironori Nakajo (PDPTA, 2006)