A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM. - Hiroaki Nambu; Kazuo Kanetani; Kaname Yamasaki; Keiichi Higeta; Masami Usami; Yasuhiro Fujimura; Kazumasa Ando; Takeshi Kusunoki; Kunihiko Yamaguchi; Noriyuki Homma (IEEE J. Solid State Circuits, 1998)

A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM. - Hiroaki Nambu; Kazuo Kanetani; Kaname Yamasaki; Keiichi Higeta; Masami Usami; Masahiko Nishiyama; Kenichi Ohhata; Fumihiko Arakawa; Takeshi Kusunoki; Kunihiko Yamaguchi; Atsuo Hotta; Noriyuki Homma (IEEE J. Solid State Circuits, 2000)

Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz. - Kenichi Ohhata; Fumihiko Arakawa; Takeshi Kusunoki; Hiroaki Nambu; Kazuo Kanetani; Kaname Yamasaki; Keiichi Higeta; Masami Usami; Masahiko Nishiyama; Kunihiko Yamaguchi; Noriyuki Homma; Atsuo Hotta (IEEE J. Solid State Circuits, 2000)

External memory BIST for system-in-package. - Kaname Yamasaki; Iwao Suzuki; Azumi Kobayashi; Keiichi Horie; Yasuharu Kobayashi; Hideyuki Aoki; Hideki Hayashi; Kenichi Tada; Koki Tsutsumida; Keiichi Higeta (ITC, 2005)

Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs. - Chizu Matsumoto; Yuichi Hamamura; Michinobu Nakao; Kaname Yamasaki; Yoshikazu Saito; Shun'ichi Kaneko (IEICE Trans. Electron., 2013)