A 4-Mb pseudo SRAM operating at 2.6+or-1 V with 3- mu A data retention current. - Katsuyuki Sato; Kanehide Kenmizaki; Shoji Kubono; Toshio Mochizuki; Hidetomo Aoyagi; Michitaro Kanamitsu; Soichi Kunito; Hiroyuki Uchida; Yoshihiko Yasu; Atsushi Ogishima; Sho Sano; Hiroshi Kawamoto (IEEE J. Solid State Circuits, 1991)