A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme. - Kang-Deog Suh; Byung-Hoon Suh; Young-Ho Lim; Jin-Ki Kim; Young-Joon Choi; Yong-Nam Koh; Sung-Soo Lee; Suk-Chon Kwon; Byung-Soon Choi; Jin-Sun Yum; Jung-Hyuk Choi; Jang-Rae Kim; et al. (IEEE J. Solid State Circuits, 1995)

A 117-mm2 3.3-V only 128-Mb multilevel NAND flash memory for mass storage applications. - Tae-Sung Jung; Young-Joon Choi; Kang-Deog Suh; Byung-Hoon Suh; Jin-Ki Kim; Young-Ho Lim; Yong-Nam Koh; Jong-Wook Park; Ki-Jong Lee; Jung-Hoon Park; Kee-Tae Park; Jhang-Rae Kim; et al. (IEEE J. Solid State Circuits, 1996)

A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using a NAND flash memory technology. - Tae-Sung Jung; Do-Chan Choi; Sung-Hee Cho; Myong-Jae Kim; Seung-Keun Lee; Byung-Soon Choi; Jin-Sun Yum; San-Hong Kim; Dong-Gi Lee; Jong-Chang Son; Myung-Sik Yong; Heung-Kwun Oh; et al. (IEEE J. Solid State Circuits, 1997)

A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed. - Jin-Ki Kim; Koji Sakui; Sung-Soo Lee; Yasuo Itoh; Suk-Chon Kwon; Kazuhisa Kanazawa; Ki-Jun Lee; Hiroshi Nakamura; Kang-Young Kim; Toshihiko Himeno; Jang-Rae Kim; Kazushige Kanda; et al. (IEEE J. Solid State Circuits, 1997)

An 8-bit-resolution, 360-μs write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS). - Kyu-Hyoun Kim; Kwyro Lee; Tae-Sung Jung; Kang-Deog Suh (IEEE J. Solid State Circuits, 1998)

A 3.3-V, 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme. - Yeonbae Chung; Byung-Gil Jeon; Kang-Deog Suh (IEEE J. Solid State Circuits, 2000)

A 0.4-μm 3.3-V 1T1C 4-Mb nonvolatile ferroelectric RAM with fixed bitline reference voltage scheme and data protection circuit. - Byung-Gil Jeon; Mun-Kyu Choi; Yoonjong Song; Seung-Kyu Oh; Yeonbae Chung; Kang-Deog Suh; Kinam Kim (IEEE J. Solid State Circuits, 2000)

A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes. - Taehee Cho; Yeong-Taek Lee; Eun-Cheol Kim; Jin-Wook Lee; Sunmi Choi; Seungjae Lee 001; Dong-Hwan Kim; Wook-Ghee Han; Young-Ho Lim; Jae-Duk Lee; Jung-Dal Choi; Kang-Deog Suh (IEEE J. Solid State Circuits, 2001)

High-performance 1-Gb-NAND flash memory with 0.12-μm technology. - June Lee; Heung-Soo Im; Dae-Seok Byeon; Kyeong-Han Lee; Dong-Hyuk Chae; Kyong-Hwa Lee; Sang Won Hwang; Sung-Soo Lee; Young-Ho Lim; Jae-Duk Lee; Jung-Dal Choi; Young-Il Seo; et al. (IEEE J. Solid State Circuits, 2002)

A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications. - June Lee; Sung-Soo Lee; Oh-Suk Kwon; Kyeong-Han Lee; Dae-Seok Byeon; In-Young Kim; Kyoung-Hwa Lee; Young-Ho Lim; Byung-Soon Choi; Jong-Sik Lee; Wang-Chul Shin; Jeong-Hyuk Choi; et al. (IEEE J. Solid State Circuits, 2003)

Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory. - Youngsun Song; Ki-Tae Park; Myounggon Kang; Yunheub Song; Sungsoo Lee; Youngho Lim; Kang-Deog Suh (IEICE Trans. Electron., 2010)

Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control for High Program Inhibition in MLC NAND Flash Memories. - Ki-Tae Park; Youngsun Song; Myounggon Kang; Sungsoo Lee; Youngho Lim; Kang-Deog Suh; Chilhee Chung (IEEE J. Solid State Circuits, 2010)