A 3-nm FinFET 563-kbit 35.5-Mbit/mm2 Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode. - Yumito Aoyagi; Koji Nii; Makoto Yabuuchi; Tomotaka Tanaka; Kazuto Mizutani; Masaya Hamada; Yuichiro Ishii; Yen Chi Chou; Jun Cheng Liu; Chien-Yu Huang; Kang-Hui Peng; Yu-Hao Hsu; et al. (IEEE J. Solid State Circuits, 2026)