A 6.25 MHz BW 8-OSR fifth-order single-stage sigma-delta ADC. - Chang-Seob Shin; Min-Ho Yoon; Kang-Il Cho; Young-Ju Kim; Kwang-Soo Kim; Seung-Hoon Lee 006; Gil-Cho Ahn (ISCAS, 2011)

A 1.1 V 82.3dB audio ΔΣ ADC using asynchronous SAR type quantizer. - Young-min Park; Tae-In Kwon; Kang-Il Cho; Yong-Sik Kwak; Gil-Cho Ahn; Chang-Seob Shin; Myung-Jin Lee; Seung-Bin You; Ho-Jin Park (ICECS, 2012)

A digitally enhanced low-distortion delta-sigma modulator for wideband application. - Jae-Hyeon Shin; Kang-Il Cho; Gil-Cho Ahn (ISOCC, 2012)

A 72.9-dB SNDR 20-MHz BW 2-2 discrete-time sturdy MASH delta-sigma modulator using source-follower-based integrators. - Yong-Sik Kwak; Kang-Il Cho; Ho-Jin Kim; Seung-Hoon Lee 006; Gil-Cho Ahn (A-SSCC, 2017)

Analog front-end for EMG acquisition system. - Bum-Sik Chung; Hyeong-Kyu Kim; Kang-Il Cho; Ho-Jin Kim; Gil-Cho Ahn (ISOCC, 2017)

A 1.8 V 89.2 dB dynamic range delta-sigma modulator using an op-amp dynamic current biasing technique. - Yong-Sik Kwak; Kang-Il Cho; Ho-Jin Kim; Gil-Cho Ahn (IEICE Electron. Express, 2017)

A 101 dB dynamic range, 2 kHz bandwidth delta-sigma modulator with a modified feed-forward architecture. - Kang-Il Cho; Yong-Sik Kwak; Ho-Jin Kim; Gil-Cho Ahn (IEICE Electron. Express, 2018)

A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Resolution-Enhanced Sturdy MASH Delta-Sigma Modulator Using Source-Follower-Based Integrators. - Yong-Sik Kwak; Kang-Il Cho; Ho-Jin Kim; Seung-Hoon Lee 006; Gil-Cho Ahn (IEEE J. Solid State Circuits, 2018)

A 10-b 320-MS/s Dual-Residue Pipelined SAR ADC with Binary Search Current Interpolator. - Kang-Il Cho; Yong-Sik Kwak; Ho-Jin Kim; Jun-Ho Boo; Seung-Hoon Lee 006; Gil-Cho Ahn (CICC, 2019)

A 101 dB Dynamic Range Delta-Sigma Modulator Using Modified Feed-Forward Architecture for Audio Application. - Jun-Young Kil; Kang-Il Cho; Ho-Jin Kim; Jun-Ho Boo; Yong-Sik Kwak; Gil-Cho Ahn (ISOCC, 2019)

A 10-b 900-MS/s Single-Channel Pipelined-SAR ADC Using Current-Mode Reference Scaling. - Kang-Il Cho; Ho-Jin Kim; Jun-Ho Boo; Yong-Sik Kwak; Jun-Sang Park; Seung-Hoon Lee 006; Gil-Cho Ahn (A-SSCC, 2020)

A 2.2mW 12-bit 200MS/s 28nm CMOS Pipelined SAR ADC with Dynamic Register-Based High-Speed SAR Logic. - Jun-Sang Park; Je-Min Jeon; Jun-Ho Boo; Jae-Hyuk Lee; Kang-Il Cho; Ho-Jin Kim; Gil-Cho Ahn; Seung-Hoon Lee 006 (A-SSCC, 2020)

A Third-Order DT Delta-Sigma Modulator With Noise-Coupling Technique. - Tae-Gwan Kim; Kang-Il Cho; Ho-Jin Kim; Jun-Ho Boo; Yong-Sik Kwak; Gil-Cho Ahn (ISOCC, 2020)

A 0.9V 0.022mm2 103dB DR Switched-Capacitor Audio Delta-Sigma Modulator Using Input-Referred kT/C Noise Reduction Technique. - Yong-Sik Kwak; Ho-Jin Kim; Kang-Il Cho; Jun-Ho Boo; Gil-Cho Ahn (A-SSCC, 2021)

A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, -0.12% for Battery-Monitoring Applications. - Jun-Ho Boo; Kang-Il Cho; Ho-Jin Kim; Jae-Geun Lim; Yong-Sik Kwak; Seung-Hoon Lee 006; Gil-Cho Ahn (IEEE J. Solid State Circuits, 2021)

A 96dB Dynamic Range 2kHz Bandwidth 2nd Order Delta-Sigma Modulator Using Modified Feed-Forward Architecture With Delayed Feedback. - Ju-Hye Han; Kang-Il Cho; Ho-Jin Kim; Jun-Ho Boo; Jae Sang Kim; Gil-Cho Ahn (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC. - Ho-Jin Kim; Jun-Ho Boo; Kang-Il Cho; Yong-Sik Kwak; Gil-Cho Ahn (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A CMOS Analog Front-End for Hall Sensor Readout IC. - Kang-Il Cho; Jun-Ho Boo; Jae-Geun Lim; Gil-Cho Ahn (ICEIC, 2024)

A High Holding Voltage Diode-Triggered SCR for Low-Voltage ESD Application. - Sora Park; Yoonseo Choi; Sungho Lee; Kang-Il Cho (ICEIC, 2024)

A Two-Step ADC with a Separate DAC Method for Enhanced Sub-Quantizer Settling Condition. - Jae-Geun Lim; Jun-Ho Boo; Hyoung-Jung Kim; Jae-Hyuk Lee; Kang-Il Cho; Gil-Cho Ahn (ICEIC, 2025)