An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM. - Dong-Uk Lee; Kyung Whan Kim; Kwan-Weon Kim; Kang Seol Lee; Sang Jin Byeon; Jin-Hee Cho; Han Ho Jin; Sang Kyun Nam; Jaejin Lee; Jun Hyun Chun; Sung-Joo Hong (VLSIC, 2014)

Design considerations of HBM stacked DRAM and the memory architecture extension. - Dong-Uk Lee; Kang Seol Lee; Yongwoo Lee; Kyung Whan Kim; Jong-Ho Kang; Jaejin Lee; Jun Hyun Chun (CICC, 2015)

A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits. - Dong-Uk Lee; Kyung Whan Kim; Kwan-Weon Kim; Kang Seol Lee; Sang Jin Byeon; Jae-Hwan Kim; Jin-Hee Cho; Jaejin Lee; Jun Hyun Chun (IEEE J. Solid State Circuits, 2015)

22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST. - Dong-Uk Lee; Ho Sung Cho; Jihwan Kim; Young Jun Ku; Sangmuk Oh; Chul Dae Kim; Hyun Woo Kim; Wooyoung Lee; Tae-Kyun Kim 001; Tae Sik Yun; Min Jeong Kim; SeungGyeon Lim; et al. (ISSCC, 2020)