Future system-on-silicon LSI chips. - Mitsumasa Koyanagi; Hiroyuki Kurino; Kang Wook Lee 002; Katsuyuki Sakuma; Nobuaki Miyakawa; Hikotaro Itani (IEEE Micro, 1998)

Smart Vision Chip Fabricated Using Three Dimensional Integration Technology. - Hiroyuki Kurino; Masaki Nakagawa; Kang Wook Lee 002; Tomonori Nakamura; Yuusuke Yamada; Ki Tae Park; Mitsumasa Koyanagi (NIPS, 2000)

Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration. - Ji Chel Bea; Mariappan Murugesan; Yuki Ohara; Akihiro Noriki; Hisashi Kino; Kang Wook Lee 002; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

3D integration technology for 3D stacked retinal chip. - Yoshiyuki Kaiho; Yuki Ohara; Hirotaka Takeshita; Kouji Kiyoyama; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

A parallel ADC for high-speed CMOS image processing system with 3D structure. - Kouji Kiyoyama; Yuki Ohara; Kang Wook Lee 002; Y. Yang; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

Heterogeneous integration technology for MEMS-LSI multi-chip module. - Kang Wook Lee 002; Shigeyuki Kanno; Yuki Ohara; Kouji Kiyoyama; Ji Chel Bea; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack. - Yuki Ohara; Akihiro Noriki; Katsuyuki Sakuma; Kang Wook Lee 002; Mariappan Murugesan; Jichoel Bea; Fumiaki Yamada; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature. - Takafumi Fukushima; Eiji Iwata; Jichoel Bea; Mariappan Murugesan; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2010)

A block-parallel signal processing system for CMOS image sensor with three-dimensional structure. - Kouji Kiyoyama; Kang Wook Lee 002; Takafumi Fukushima; H. Naganuma; Hiroaki Kobayashi; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2010)

Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding. - Mariappan Murugesan; Yuki Ohara; Jichoel Bea; Kang Wook Lee 002; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2010)

Through Silicon photonic via (TSPV) with Si core for low loss and high-speed data transmission in opto-electronic 3-D LSI. - Akihiro Noriki; Kang Wook Lee 002; Jichoel Bea; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2010)

Temporary bonding strength control for self-assembly-based 3D integration. - Takafumi Fukushima; Yuki Ohara; Jichoel Bea; Mariappan Murugesan; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

Chip-level TSV integration for rapid prototyping of 3D system LSIs. - Kazuyuki Hozawa; Futoshi Furuta; Yuko Hanaoka; Mayu Aoki; Kenichi Takeda; Katsuyuki Sakuma; Kang Wook Lee 002; Takafumi Fukushima; Mitsumasa Koyanagi (3DIC, 2011)

A very low area ADC for 3-D stacked CMOS image processing system. - Kouji Kiyoyama; Kang Wook Lee 002; Takafumi Fukushima; H. Naganuma; H. Kobayashi; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs. - Kang Wook Lee 002; Jichoel Bea; Takafumi Fukushima; Yuki Ohara; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI. - Akihiro Noriki; Kang Wook Lee 002; Jichoel Bea; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

Novel detachable bonding process with wettability control of bonding surface for versatile chip-level 3D integration. - Yuki Ohara; Kang Wook Lee 002; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration. - Takafumi Fukushima; Takayuki Konno; Eiji Iwata; Risato Kobayashi; Toshiya Kojima; Mariappan Murugesan; Ji Chel Bea; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (Micromachines, 2011)

Development of via-last 3D integration technologies using a new temporary adhesive system. - Takafumi Fukushima; Jichoel Bea; Mariappan Murugesan; Kang Wook Lee 002; Mitsumasa Koyanagi (3DIC, 2013)

3D memory chip stacking by multi-layer self-assembly technology. - Takafumi Fukushima; Jichoel Bea; Mariappan Murugesan; Ho-Young Son; Min-Suk Suh; K.-Y. Byun; N.-S. Kim; Kang Wook Lee 002; Mitsumasa Koyanagi (3DIC, 2013)

Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system. - Hiroyuki Hashimoto; Takafumi Fukushima; Kang Wook Lee 002; Mitsumasa Koyanagi; Tetsu Tanaka (3DIC, 2013)

A block-parallel ADC with digital noise cancelling for 3-D stacked CMOS image sensor. - Kouji Kiyoyama; Y. Sato; Hiroyuki Hashimoto; Kang Wook Lee 002; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2013)

Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory. - Kang Wook Lee 002; Seiya Tanikawa; Mariappan Murugesan; H. Naganuma; Jichoel Bea; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2013)

Effect of CVD Mn oxide layer as Cu diffusion barrier for TSV. - Mariappan Murugesan; Jichoel Bea; Kang Wook Lee 002; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi; Yuji Sutou; H. Wang; J. Koike (3DIC, 2013)

Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration. - Takafumi Fukushima; Yuka Ito; Mariappan Murugesan; Jicheol Bea; Kang Wook Lee 002; Koji Choki; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2014)

Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding. - Takafumi Fukushima; Taku Suzuki; Hideto Hashiguchi; Chisato Nagai; Jichoel Bea; Hiroyuki Hashimoto; Mariappan Murugesan; Kang Wook Lee 002; Tetsu Tanaka; Kazushi Asami; Yasuhiro Kitamura; Mitsumasa Koyanagi (3DIC, 2015)

Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications. - Yangyang Yan; Yingtao Ding; Qianwen Chen; Kang Wook Lee 002; Takafumi Fukushima; Mitsumasa Koyanagi (3DIC, 2015)

Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM. - Kang Wook Lee 002; Ji Chel Bea; Mariappan Murugesan; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (IRPS, 2015)

New concept of TSV formation methodology using Directed Self-Assembly (DSA). - Takafumi Fukushima; Mariappan Murugesan; Shin Ohsaki; Hiroyuki Hashimoto; Jichoel Bea; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2016)

Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications. - Kang Wook Lee 002; Ai Nakamura; Jicheol Bea; Takafumi Fukushima; Suresh Ramalingam; Xin Wu; Tanaka Tanaka; Mitsumasa Koyanagi (3DIC, 2016)

Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration. - Takafumi Fukushima; Hideto Hashiguchi; Hiroshi Yonekura; Hisashi Kino; Mariappan Murugesan; Ji Chel Bea; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (Micromachines, 2016)