Level Selection Based 4-PAM Transmitter for Chip to Chip Communication. - Kang-Yu Chang; Zhi-Ming Lin (APCCAS, 2006)

Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays. - Yu-Cheng Su; Kang-Yu Chang; Yu-Tung Chin; Chia-Wen Chang; Shyh-Jye Jou (ASICON, 2019)

On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. - Hung-Ming Chen; Chia-Lin Hu; Kang-Yu Chang; Alexandra Küster; Yu-Hsien Lin; Po-Shen Kuo; Wei-Tung Chao; Bo-Cheng Lai; Chien-Nan Liu; Shyh-Jye Jou (ICCAD, 2020)

A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO. - Chia-Chen Chang; Yu-Tung Chin; Hossameldin A. Ibrahim; Kang-Yu Chang; Shyh-Jye Jou (ISCAS, 2021)

On Reconfiguring Memory-Centric AI Edge Devices for CIM. - Hung-Ming Chen; Cheng-En Ni; Kang-Yu Chang; Tzu-Chieh Chiang; Shih-Han Chang; Cheng-Yu Chiang; Bo-Cheng Lai; Chien-Nan Liu; Shyh-Jye Jou (ISOCC, 2021)

A Reconfigurable In-SRAM Computing Architecture for DCNN Applications. - Yu-Hsien Lin; Chi Liu; Chia-Lin Hu; Kang-Yu Chang; Jia-Yin Chen; Shyh-Jye Jou (VLSI-DAT, 2021)

On Optimizing Capacitor Array Design for Advanced Node SAR ADC. - Cheng-Yu Chiang; Chia-Lin Hu; Kang-Yu Chang; Mark Po-Hung Lin; Shyh-Jye Jou; Hung-Yu Chen; Chien-Nan Jimmy Liu; Hung-Ming Chen (SMACD, 2022)

An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. - Chi Liu; Shao-Tzu Li; Tong-Lin Pan; Cheng-En Ni; Yun Sung; Chia-Lin Hu; Kang-Yu Chang; Tuo-Hung Hou; Tian-Sheuan Chang; Shyh-Jye Jou (VLSI-DAT, 2022)