A multi-phase detecting method for spurs cancellation in all digital fractional-N phase-lock loops. - Tingbing Ouyang; Kanglin Xiao; Xiaoqi Lin; Changpei Qiu; Bo Wang 016 (MWSCAS, 2018)

A balanced hybrid ring oscillator for precise temperature compensation. - Kanglin Xiao; Bo Wang 016; Xiaoqi Lin; Changpei Qiu (MWSCAS, 2018)

Improved Discrete Wavelet Analysis and Principal Component Analysis for EEG Signal Processing. - Yi-Hsiang Chen; Xiaoxin Cui; Kanglin Xiao; Dunshan Yu (ASICON, 2019)

BNReLU: Combine Batch Normalization and Rectified Linear Unit to Reduce Hardware Overhead. - Jiexian Ge; Xiaoxin Cui; Kanglin Xiao; Chenglong Zou; Yi-Hsiang Chen; Rongshan Wei (ASICON, 2019)

An SNN-Based and Neuromorphic-Hardware-Implementable Noise Filter with Self-adaptive Time Window for Event-Based Vision Sensor. - Kanglin Xiao; Xiaoxin Cui; Kefei Liu 002; Xiaole Cui; Xin'an Wang (IJCNN, 2021)

Design and Implementation of a Temperature Self-Compensation Balanced Hybrid Ring Oscillator BHRO. - Kanglin Xiao; Bo Wang 016; Changpei Qiu; Xin'an Wang (ISCAS, 2021)

A Full-Neuron Memory Model Designed for Neuromorphic Systems. - Kefei Liu 002; Xiaoxin Cui; Chenglong Zou; Yisong Kuang; Yi Zhong; Kanglin Xiao; Yuan Wang 001 (AICAS, 2022)

A Reconfigurable SRAM Computing-in-Memory Macro Supporting Ping-Pong Operation and CIM pipeline for Multi-mode MAC operations. - Kanglin Xiao; Xiaoxin Cui; Xin Qiao; Xin'an Wang; Yuan Wang 001 (ICTA, 2022)

A 28nm 64Kb SRAM based Inference-Training Tri-Mode Computing-in-Memory Macro. - Nanbing Pan; Xiaoxin Cui; Xin Qiao; Kanglin Xiao; Qingyu Guo; Yuan Wang 001 (ISCAS, 2022)

A Computing-in-Memory SRAM Macro Based on Fully-Capacitive-Coupling With Hierarchical Capacity Attenuator for 4-b MAC Operation. - Kanglin Xiao; Xiaoxin Cui; Xin Qiao; Nanbing Pan; Xin'an Wang; Yuan Wang 001 (ISCAS, 2022)

A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications. - Kanglin Xiao; Xiaoxin Cui; Xin Qiao; Xin'an Wang; Yuan Wang 001 (Microelectron. J., 2022)

Real-Time Target Tracking System With Spiking Neural Networks Implemented on Neuromorphic Chips. - Kefei Liu 002; Xiaoxin Cui; Xiang Ji; Yisong Kuang; Chenglong Zou; Yi Zhong; Kanglin Xiao; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation. - Kanglin Xiao; Xiaoxin Cui; Xin Qiao; Jiahao Song; Haoyang Luo; Xin'an Wang; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

How the Brain Achieves Real-Time Vision: A Spiking Position Perception Model. - Kefei Liu 002; Jingjie Shang; Xiaoxin Cui; Chenglong Zou; Yisong Kuang; Kanglin Xiao; Yi Zhong; Yuan Wang 001 (IEEE Trans. Cogn. Dev. Syst., 2024)

A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations. - Kanglin Xiao; Xin Qiao; Xiaoxin Cui; Jiahao Song; Haoyang Luo; Xin'an Wang; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)