A comparative performance analysis of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye simulator. - Kangmin Lee; Chi Weon Yoon; Ramchan Woo; Jeong-Hun Kook; Ja-Il Koo; Tae-Sung Jung; Hoi-Jun Yoo (ISCAS (5), 2001)

An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications. - Chi Weon Yoon; Ramchan Woo; Jeengheon Kook; Se-Joong Lee; Kangmin Lee; Hoi-Jun Yeo (IEEE J. Solid State Circuits, 2001)

A practical method to use eDRAM in the shared bus packet switch. - Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (GLOBECOM, 2002)

A distributed crossbar switch scheduler for on-chip networks. - Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (CICC, 2003)

A high-speed and lightweight on-chip crossbar switch scheduler for on-chip interconnection networks. - Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (ESSCIRC, 2003)

A 10Gbps/port 8×8 shared bus switch with embedded DRAM hierarchical output buffer. - Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (ESSCIRC, 2003)

SILENT: serialized low energy transmission coding for on-chip interconnection networks. - Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (ICCAD, 2004)

On-chip network based embedded core testing. - Jong-Sun Kim; Min-Su Hwang; Seungsu Roh; Ja-Young Lee; Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (SoCC, 2004)

Low energy transmission coding for on-chip serial communications. - Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (SoCC, 2004)

An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip. - Kwanho Kim; Se-Joong Lee; Kangmin Lee; Hoi-Jun Yoo (ISCAS (3), 2005)

A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip. - Donghyun Kim; Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (ISCAS (3), 2005)

Analysis and Implementation of Practical, Cost-Effective Networks on Chips. - Se-Joong Lee; Kangmin Lee; Hoi-Jun Yoo (IEEE Des. Test Comput., 2005)

Packet-switched on-chip interconnection network for system-on-chip applications. - Se-Joong Lee; Kangmin Lee; Seong-Jun Song; Hoi-Jun Yoo (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

A 372 ps 64-bit adder using fast pull-up logic in 0.18µm CMOS. - Joo-Young Kim 001; Kangmin Lee; Hoi-Jun Yoo (ISCAS, 2006)

Low-power network-on-chip for high-performance SoC design. - Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo (IEEE Trans. Very Large Scale Integr. Syst., 2006)

MAEPER: Matching Access and Error Patterns With Error-Free Resource for Low Vcc L1 Cache. - Young-Geun Choi; Sungjoo Yoo; Sunggu Lee; Jung Ho Ahn; Kangmin Lee (IEEE Trans. Very Large Scale Integr. Syst., 2013)

ParaTM: Transparent Embedding of Hardware Transactional Memory for Traditional Applications. - Kangmin Lee; Heeseung Jo (IEEE Access, 2018)

Timing offset independent PSCCH detection method for 5G-NR V2X SL systems. - Jonggyu Oh; Ki-Young Kwak; Kangmin Lee (ICCE, 2024)

MAGIC: A Multi-Hop and Graph-Based Benchmark for Inter-Context Conflicts in Retrieval-Augmented Generation. - Jungyeon Lee; Kangmin Lee; Taeuk Kim (CoRR, 2025)