A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation. - Kyunghoon Kim; Joo-Hyung Chae; Jaehyeok Yang; Jihyo Kang; Gang-Sik Lee; Sang-Yeon Byeon; Youngtaek Kim; Boram Kim; Dong-Hyun Kim; Yeongmuk Cho; Kangmoo Choi; Hyeongyeol Park; et al. (ISSCC, 2021)