A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits. - Kangning Wang 004; Huidong Zhao; Jiliang Liu; Jialu Yin; Zhi Li 090; Shushan Qiao (IEICE Electron. Express, 2023)

An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS. - Jiliang Liu; Huidong Zhao; Zhi Li 090; Kangning Wang 004; Shushan Qiao (IEEE Access, 2024)

A dynamic voltage scaling circuit design based on critical path replica and time warning techniques. - Ji-liang Liu; Kangning Wang 004; Jia-lu Yin; Xue-long Zhao; Zhi Li 090; Hui-dong Zhao; Shushan Qiao (IEICE Electron. Express, 2024)

AO-EDC: An Accuracy-Oriented Error Detection and Correction Scheme for DVFS System Based on Propagation Detection at Half-Path Points. - Zitao Liang; Jiliang Liu; Kangning Wang 004; Linnan Li; Zhi Li 090; Huidong Zhao; Shushan Qiao (ISCAS, 2025)

Erratum: A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits [IEICE Electronics Express Vol. 20 (2023) No. 11 pp. 20230145]. - Kangning Wang 004; Huidong Zhao; Jiliang Liu; Jialu Yin; Zhi Li 090; Shushan Qiao (IEICE Electron. Express, 2025)

A Self-Calibrated Unified Voltage-and-Frequency Regulator System Design Based on Universal Logic Line Circuit. - Jiliang Liu; Huidong Zhao; Zhi Li 090; Kangning Wang 004; Shushan Qiao (IEEE Trans. Very Large Scale Integr. Syst., 2025)

ITP-PAD: A Timing Monitoring Mechanism for AVS Systems Using Intersection Timing Prediction and Path Activation Detection. - Kangning Wang 004; Huidong Zhao; Zhi Li 090; Jiliang Liu; Shushan Qiao (IEEE Trans. Circuits Syst. II Express Briefs, 2025)