Integration of dual channel timing formatter system for high speed memory test equipment. - Jaeseok Park; Ingeol Lee; Young-Seok Park; Sung-Geun Kim; Kyungho Ryu; Dong-Hoon Jung; Kangwook Jo; Choong Keun Lee; Hongil Yoon; Seong-Ook Jung; Woo-Young Choi; Sungho Kang 001 (ISOCC, 2012)

Variation-tolerant and low power look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile field programmable gate array (FPGA). - Kangwook Jo; Kyungseon Cho; Hongil Yoon (ISOCC, 2016)

Variation-Tolerant Sensing Circuit for Ultralow-Voltage Operation of Spin-Torque Transfer Magnetic RAM. - Kangwook Jo; Hongil Yoon (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique. - Hwang Huh; Wanik Cho; Jinhaeng Lee; Yujong Noh; Yongsoon Park; Sunghwa Ok; Jongwoo Kim; Kayoung Cho; Hyunchul Lee; Geonu Kim; Kangwoo Park; Kwanho Kim; et al. (ISSCC, 2020)

A High-Performance 1Tb 3b/Cell 3D-NAND Flash with a 194MB/s Write Throughput on over 300 Layers $ mathsf{i}$. - Bvunarvul Kim; Seungpil Lee; Beomseok Hah; Kanawoo Park; Yongsoon Park; Kangwook Jo; Yujong Noh; Hyeon-Cheon Seol; Hyunsoo Lee; Jae-Hyeon Shin; Seongjin Choi; Youngdon Jung; et al. (ISSCC, 2023)