Fast performance analysis of bus-based system-on-chip communication architectures. - Kanishka Lahiri; Anand Raghunathan; Sujit Dey (ICCAD, 1999)

Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. - Kanishka Lahiri; Anand Raghunathan; Ganesh Lakshminarayana; Sujit Dey (DAC, 2000)

Efficient Exploration of the SoC Communication Architecture Design Space. - Kanishka Lahiri; Anand Raghunathan; Sujit Dey (ICCAD, 2000)

Performance Analysis of Systems with Multi-Channel Communication Architectures. - Kanishka Lahiri; Sujit Dey; Anand Raghunathan (VLSI Design, 2000)

LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. - Kanishka Lahiri; Anand Raghunathan; Ganesh Lakshminarayana (DAC, 2001)

Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. - Kanishka Lahiri; Sujit Dey; Anand Raghunathan (VLSI Design, 2001)

Battery Life Estimation of Mobile Embedded Systems. - Debashis Panigrahi; Sujit Dey; Ramesh R. Rao; Kanishka Lahiri; Carla-Fabiana Chiasserini; Anand Raghunathan (VLSI Design, 2001)

System-level performance analysis for designing on-chipcommunication architectures. - Kanishka Lahiri; Anand Raghunathan; Sujit Dey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Fast system-level power profiling for battery-efficient system design. - Kanishka Lahiri; Anand Raghunathan; Sujit Dey (CODES, 2002)

Communication architecture based power management for battery efficient system design. - Kanishka Lahiri; Sujit Dey; Anand Raghunathan (DAC, 2002)

Battery-efficient architecture for an 802.11 MAC processor. - Kanishka Lahiri; Anand Raghunathan; Sujit Dey (ICC, 2002)

Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design. - Kanishka Lahiri; Anand Raghunathan; Sujit Dey; Debashis Panigrahi (ASP-DAC/VLSI Design, 2002)

Communication-Based Power Management. - Kanishka Lahiri; Sujit Dey; Anand Raghunathan (IEEE Des. Test Comput., 2002)

Dynamic Platform Management for Configurable Platform-Based System-on-Chips. - Krishna Sekar; Kanishka Lahiri; Sujit Dey (ICCAD, 2003)

Power analysis of system-level on-chip communication architectures. - Kanishka Lahiri; Anand Raghunathan (CODES+ISSS, 2004)

Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips. - Krishna Sekar; Kanishka Lahiri; Sujit Dey (VLSI Design, 2004)

Efficient power profiling for battery-driven embedded system design. - Kanishka Lahiri; Anand Raghunathan; Sujit Dey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Design space exploration for optimizing on-chip communication architectures. - Kanishka Lahiri; Anand Raghunathan; Sujit Dey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Design of high-performance system-on-chips using communication architecture tuners. - Kanishka Lahiri; Anand Raghunathan; Ganesh Lakshminarayana; Sujit Dey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. - Krishna Sekar; Kanishka Lahiri; Anand Raghunathan; Sujit Dey (DAC, 2005)

SOFTENIT: a methodology for boosting the software content of system-on-chip designs. - Abhishek Mitra; Marcello Lajolo; Kanishka Lahiri (ACM Great Lakes Symposium on VLSI, 2005)

Battery discharge characteristics of wireless sensor nodes: an experimental analysis. - Chulsung Park; Kanishka Lahiri; Anand Raghunathan (SECON, 2005)

Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. - Nikhil Bansal 003; Kanishka Lahiri; Anand Raghunathan; Srimat T. Chakradhar (VLSI Design, 2005)

Signature-based workload estimation for mobile 3D graphics. - Bren Mochocki; Kanishka Lahiri; Srihari Cadambi; Xiaobo Sharon Hu (DAC, 2006)

Power analysis of mobile 3D graphics. - Bren Mochocki; Kanishka Lahiri; Srihari Cadambi (DATE, 2006)

Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms. - Krishna Sekar; Kanishka Lahiri; Anand Raghunathan; Sujit Dey (DATE, 2006)

Adaptive data placement in an embedded multiprocessor thread library. - Phillip Stanley-Marbell; Kanishka Lahiri; Anand Raghunathan (DATE, 2006)

Considering process variations during system-level power analysis. - Saumya Chandra; Kanishka Lahiri; Anand Raghunathan; Sujit Dey (ISLPED, 2006)

The LOTTERYBUS on-chip communication architecture. - Kanishka Lahiri; Anand Raghunathan; Ganesh Lakshminarayana (IEEE Trans. Very Large Scale Integr. Syst., 2006)

System-on-Chip Power Management Considering Leakage Power Variations. - Saumya Chandra; Kanishka Lahiri; Anand Raghunathan; Sujit Dey (DAC, 2007)

Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation. - Mohammad Ali Ghodrat; Kanishka Lahiri; Anand Raghunathan (DAC, 2007)

Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis. - Nikhil Bansal 003; Kanishka Lahiri; Anand Raghunathan (VLSI Design, 2007)

Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. - Nikil D. Dutt; Kaustav Banerjee; Luca Benini; Kanishka Lahiri; Sudeep Pasricha (VLSI Design, 2007)

Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication. - Krishna Sekar; Kanishka Lahiri; Anand Raghunathan; Sujit Dey (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Variation-Tolerant Dynamic Power Management at the System-Level. - Saumya Chandra; Kanishka Lahiri; Anand Raghunathan; Sujit Dey (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Variation-Aware System-Level Power Analysis. - Saumya Chandra; Kanishka Lahiri; Anand Raghunathan; Sujit Dey (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Characterizing Large Dataset GPU Compute Workloads Targeting Systems with Die-Stacked Memory. - Srividya Ramanathan; Gautam Hazari; Kanishka Lahiri; Francesco Spadini (HiPC, 2015)

DARTS: Performance-counter driven sampling using binary translators. - Rajesh Kumar; Suchita Pati; Kanishka Lahiri (ISPASS, 2017)

Fast IPC estimation for performance projections using proxy suites and decision trees. - Kanishka Lahiri; Subhash Kunnoth (ISPASS, 2017)

Performance Scaling of Cassandra on High-Thread Count Servers. - Disha Talreja; Kanishka Lahiri; Subramaniam Kalambur; Prakash Raghavendra (ICPE, 2019)

Characterizing the Scale-Up Performance of Microservices using TeaStore. - Sriyash Caculo; Kanishka Lahiri; Subramaniam Kalambur (IISWC, 2020)