Functional verification of memory circuits from mask artwork data. - Masahiko Kawamura; Haruo Takagi; Kanji Hirabayashi (DAC, 1984)

AFS : An Approximate Fault Simulator. - Masahiko Kawamura; Kanji Hirabayashi (ITC, 1985)

Test generation by activation and defect-drive (TEGAD). - Susumu Nitta; Masahiko Kawamura; Kanji Hirabayashi (Integr., 1985)

Probabilistic fault grading based on activation checking and observability analysis. - Masahisa Nakazawa; Susumu Nitta; Kanji Hirabayashi (J. Electron. Test., 1990)

Self-checking CMOS circuits using pass-transistor logic. - Kanji Hirabayashi (J. Electron. Test., 1991)

Delay fault simulation of sequential circuits. - Kanji Hirabayashi (J. Electron. Test., 1993)

A parametric yield model. - Kanji Hirabayashi (J. Electron. Test., 1995)

Hazard simulation of sequential circuits. - Kanji Hirabayashi (J. Electron. Test., 1996)

A Method of Formal Verification of Cryptographic Circuits. - Kanji Hirabayashi (J. Electron. Test., 1998)

An Algebraic Approach to Formal Verification of Microprocessors. - Kanji Hirabayashi (J. Electron. Test., 2001)