Geometric Tiling for Reducing Power Consumption in Structured Matrix Operations. - G. Chen; Liping Xue; Jungsub Kim; Kanwaldeep Sobti; Lanping Deng; Xiaobai Sun; Nikos Pitsianis; Chaitali Chakrabarti; Mahmut T. Kandemir; Narayanan Vijaykrishnan (SoCC, 2006)

TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms. - Jungsub Kim; Prasanth Mangalagiri; Kevin M. Irick; Mahmut T. Kandemir; Vijaykrishnan Narayanan; Kanwaldeep Sobti; Lanping Deng; Chaitali Chakrabarti; Nikos Pitsianis; Xiaobai Sun (FPL, 2007)

Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations. - Kanwaldeep Sobti; Lanping Deng; Chaitali Chakrabarti; Nikos Pitsianis; Xiaobai Sun; Jungsub Kim; Prasanth Mangalagiri; Kevin M. Irick; Mahmut T. Kandemir; Vijaykrishnan Narayanan (SiPS, 2007)

Accurate models for estimating area and power of FPGA implementations. - Lanping Deng; Kanwaldeep Sobti; Chaitali Chakrabarti (ICASSP, 2008)

An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization. - Jungsub Kim; Lanping Deng; Prasanth Mangalagiri; Kevin M. Irick; Kanwaldeep Sobti; Mahmut T. Kandemir; Vijaykrishnan Narayanan; Chaitali Chakrabarti; Nikos Pitsianis; Xiaobai Sun (IEEE Trans. Computers, 2009)

The scan-DFT features of AMD's next-generation microprocessor core. - Mahmut Yilmaz; Baosheng Wang; Jayalakshmi Rajaraman; Tom Olsen; Kanwaldeep Sobti; Dwight Elvey; Jeff Fitzgerald; Grady Giles; Wei-Yu Chen (ITC, 2010)

Structural tests of slave clock gating in low-power flip-flop. - Baosheng Wang; Jayalakshmi Rajaraman; Kanwaldeep Sobti; Derrick Losli; Jeff Rearick (VTS, 2011)

Accurate Area, Time and Power Models for FPGA-Based Implementations. - Lanping Deng; Kanwaldeep Sobti; Yuanrui Zhang; Chaitali Chakrabarti (J. Signal Process. Syst., 2011)