Timing optimization of combinational logic. - Kanwar Jit Singh; Albert R. Wang; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1988)

A Heuristic Algorithm for the Fanout Problem. - Kanwar Jit Singh; Alberto L. Sangiovanni-Vincentelli (DAC, 1990)

Performance Optimization of Pipelined Circuits. - Sharad Malik; Kanwar Jit Singh; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1990)

On the Temporal Equivalence of Sequential Circuits. - Narendra V. Shenoy; Kanwar Jit Singh; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1992)

Sequential Circuit Design Using Synthesis and Optimization. - Ellen Sentovich; Kanwar Jit Singh; Cho W. Moon; Hamid Savoj; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCD, 1992)

Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. - Sharad Malik; Kanwar Jit Singh; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

A 200-mW, 3.3-V, CMOS color camera IC producing 352×288 24-b video at 30 frames/s. - Marc J. Loinaz; Kanwar Jit Singh; Andrew J. Blanksby; David A. Inglis; Kamran Azadet; Bryan D. Ackland (IEEE J. Solid State Circuits, 1998)

Software Environment for a Multiprocessor DSP. - Asawaree Kalavade; Joe Othmer; Bryan D. Ackland; Kanwar Jit Singh (DAC, 1999)

A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP. - Bryan D. Ackland; A. Anesko; D. Brinthaupt; S. J. Daubert; Asawaree Kalavade; J. Knobloch; E. Micca; M. Moturi; Chris J. Nicol; Jay H. O'Neill; Joe Othmer; Eduard Sackinger; et al. (IEEE J. Solid State Circuits, 2000)