Improve DRAM Leakage Issue During RAS Operational Phase Through TCAD Simulation. - Ning Li; Wen-Yang Jiang; Blacksmith Wu; Kanyu Cao (ASICON, 2019)

Improved Model for ESD Failure Caused by Stressing No Connect Pin. - Jingrui Ma; Qi-An Xu; Blacksmith Wu; Kanyu Cao (ASICON, 2019)

Adaptive OCD and ODT Control for Channel S/I Enhancement in DDR4 SDRAM. - Yanwu Du; Chris Eom; Jake Jung; Brian Lee 003; Edwin Kim; Kanyu Cao (ASICON, 2021)

A 2-stage with 3-stack 1-tap DFE Sense Amplifier based on Dual Reference for High Speed & Low Power DRAM Interface. - Yinchuan Gu; Chris Eom; Jake Jung; Brian Lee 003; Edwin Kim; Kanyu Cao (ASICON, 2021)

Adaptive DLL Update Scheme for Power Fluctuation Immunity Using Phase Error Detector. - Siman Li; Chris Eom; Jake Jung; Brian Lee 003; Edwin Kim; Kanyu Cao (ASICON, 2021)

Impact of Hydrogen Anneal on Peripheral PMOS NBTI and Array Transistor GIDL in DRAM. - Xiong Li; Huangxia Zhu; Xiaolin Guo; Kejun Mu; Peng Feng; Qi-An Xu; Blacksmith Wu; Kanyu Cao (ASICON, 2021)

Pitch Device Design in 10nm-Class DRAM Process through DTCO. - Yanzhe Tang; Zhongming Liu; Weibing Shang; Fengqin Zhang; Bernard Wu; Zhong Kong; Hongwen Li; Hong Ma; Kanyu Cao (ASICON, 2021)

Dielectric Relaxation Performance of DRAM Storage Capacitors and Ways of Improvement. - Z. Asher Bai; Yixian Wang; Lixue Liu; Xi Zhang; Feng Yuan; Junsheng Meng; Zhongming Liu; Js Jeon; James Cho; Blacksmith Wu; Huihui Li; Guilei Wang; et al. (IMW, 2023)

Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation. - Longda Zhou; Jie Li; Zheng Qiao; Pengpeng Ren; Zixuan Sun; Jianping Wang; Blacksmith Wu; Zhigang Ji; Runsheng Wang; Kanyu Cao; Ru Huang 001 (IRPS, 2023)

Sub-20-nm DRAM Technology under Negative Bias Temperature Instability (NBTI): from Characterization to Physical Origin Identification. - Da Wang; Yongkang Xue; Yong Liu; Pengpeng Ren; Zixuan Sun; Zirui Wang; Yueyang Liu; Zhijun Cheng; Haiyang Yang; Xiangli Liu; Blacksmith Wu; Kanyu Cao; et al. (IRPS, 2024)