Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOI. - Jyi-Tsong Lin; Yi-Chuen Eng; Tai-Yi Lee; Kao-Cheng Lin (VLSI Design, 2007)

17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies. - Hidehiro Fujiwara; Li-Wen Wang; Yen-Huei Chen; Kao-Cheng Lin; Dar Sun; Shin-Rung Wu; Jhon-Jhy Liaw; Chih-Yung Lin; Mu-Chi Chiang; Hung-Jen Liao; Shien-Yang Wu; Jonathan Chang (ISSCC, 2015)

A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications. - Yen-Huei Chen; Kao-Cheng Lin; Ching-Wei Wu; Wei-Min Chan; Jhon-Jhy Liaw; Hung-Jen Liao; Jonathan Chang (VLSI Circuits, 2016)

12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. - Jonathan Chang; Yen-Huei Chen; Wei-Min Chan; Sahil Preet Singh; Hank Cheng; Hidehiro Fujiwara; Jih-Yu Lin; Kao-Cheng Lin; John Hung; Robin Lee; Hung-Jen Liao; Jhon-Jhy Liaw; et al. (ISSCC, 2017)

A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue. - Hidehiro Fujiwara; Chih-Yu Lin; Hsien-Yu Pan; Cheng-Han Lin; Po-Yi Huang; Kao-Cheng Lin; Jhon-Jhy Liaw; Yen-Huei Chen; Hung-Jen Liao; Jonathan Chang (ISSCC, 2019)