An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3. - Chiyoji Tanaka; Shinichi Murai; Hiroo Tsuji; Toshihiko Yahara; Kaoru Okazaki; Masayuki Terai; Reiji Katoh; Mikio Tachibana (DAC, 1981)

Efficient Logic Verification and Test Validation for MOS LSI Circuits. - Kaoru Okazaki; Toshihiko Yahara (ITC, 1981)

A multiple media delay simulator for MOS LSI circuits. - Kaoru Okazaki; Tomoko Moriya; Toshihiko Yahara (DAC, 1983)

Delay-Time Modeling for ED MOS Logic LSI. - Takeshi Tokuda; Kaoru Okazaki; Kazuhiro Sakashita; Isao Ohkura; Tatsuya Enomoto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

A CMOS cell generation system for two-dimensional transistor placement. - Satoshi Shibatani; Toshiyuki Sadakane; Hiroomi Nakao; Masayuki Terai; Kaoru Okazaki (CICC, 1998)

A new router for reducing "antenna effect" in ASIC design. - Hiroshi Shirota; Toshiyuki Sadakane; Masayuki Terai; Kaoru Okazaki (CICC, 1998)