An integrated switched-capacitor signal processing design system. - Allen R. Barlow; Kaoru Takasuka; Yasunori Nambu; Toshio Adachi; Jun-Ichi Konno; Mineo Nishimoto; Shiro Suzuki; Kenji Nemoto; Kohji Takashima (IEEE J. Solid State Circuits, 1990)

Analogue EHW Chip for Intermediate Frequency Filters. - Masahiro Murakawa; Shuji Yoshizawa; Toshio Adachi; Shiro Suzuki; Kaoru Takasuka; Masaya Iwata; Tetsuya Higuchi (ICES, 1998)

An Evolutionary Approach to GHz Digital Systems. - Neil Marston; Eiichi Takahashi; Masahiro Murakawa; Yuji Kasai; Tetsuya Higuchi; Toshio Adachi; Kaoru Takasuka (Evolvable Hardware, 2000)

An AI-calibrated IF filter: a yield enhancement method with area and power dissipation reductions. - Masahiro Murakawa; Toshio Adachi; Yoshihiro Nino; Eiichi Takahashi; Yuji Kasai; Kaoru Takasuka; Tetsuya Higuchi (CICC, 2002)

An AI-calibrated IF filter: a yield enhancement method with area and power dissipation reductions. - Masahiro Murakawa; Toshio Adachi; Yoshihiro Niino; Yuji Kasai; Eiichi Takahashi; Kaoru Takasuka; Tetsuya Higuchi (IEEE J. Solid State Circuits, 2003)

A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators. - Gil-Cho Ahn; Dong-Young Chang; Matthew E. Brown; Naoto Ozaki; Hiroshi Youra; Ken Yamamura; Koichi Hamashita; Kaoru Takasuka; Gábor C. Temes; Un-Ku Moon (IEEE J. Solid State Circuits, 2005)

A 3V 110µW 3.1 ppm/°C curvature-compensated CMOS bandgap reference. - Xiaokang Guan; Albert Z. Wang; Akira Ishikawa; Satoru Tamura; Kaoru Takasuka; Zhihua Wang 001; Chun Zhang (ISCAS, 2006)

An Image Rejection Mixer with AI-Based Improved Performance for WCDMA Applications. - Yuji Kasai; Kiyoshi Miyashita; Hidenori Sakanashi; Eiichi Takahashi; Masaya Iwata; Masahiro Murakawa; Kiyoshi Watanabe; Yukihiro Ueda; Kaoru Takasuka; Tetsuya Higuchi (IEICE Trans. Electron., 2006)

Design of a rugged 60 V VDMOS transistor. - Edward Xu; Olivier Trescases; I-Shan Michael Sun; Dora Lee; Wai Tung Ng; Kenji Fukumoto; Akira Ishikawa; Yuichi Furukawa; Hisaya Imai; Takashi Naito; Nobuyuki Sato; Satoru Tamura; et al. (IET Circuits Devices Syst., 2007)

A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR. - Kyehyung Lee; Jeongseok Chae; Mitsuru Aniya; Koichi Hamashita; Kaoru Takasuka; Seiji Takeuchi; Gabor C. Temes (ISSCC, 2008)

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, -98 dB THD, and 79 dB SNDR. - Kyehyung Lee; Jeongseok Chae; Mitsuru Aniya; Koichi Hamashita; Kaoru Takasuka; Seiji Takeuchi; Gabor C. Temes (IEEE J. Solid State Circuits, 2008)

A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver. - Kyehyung Lee; Qingdong Meng; Tetsuro Sugimoto; Koichi Hamashita; Kaoru Takasuka; Seiji Takeuchi; Un-Ku Moon; Gabor C. Temes (IEEE J. Solid State Circuits, 2009)

A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback. - Naga Sasidhar; Youn-Jae Kook; Seiji Takeuchi; Koichi Hamashita; Kaoru Takasuka; Pavan Kumar Hanumolu; Un-Ku Moon (IEEE J. Solid State Circuits, 2009)