Process variation tolerant 9T SRAM bitcell design. - G. K. Reddy; Kapil Jainwal; Jawar Singh; Saraju P. Mohanty (ISQED, 2012)

A high background light subtraction circuit for long range time-of-flight cameras. - Chandani Anand; Kapil Jainwal; Mukul Sarkar (APCCAS, 2016)

Design of a hybrid ring oscillator at 1.5/3.0 GHz with low power supply sensitivity. - Vivek Sharma 002; Kapil Jainwal; Abhishek Tripathi (APCCAS, 2016)

A Three-Phase, One-Tap High Background Light Subtraction Time-of-Flight Camera. - Chandani Anand; Kapil Jainwal; Mukul Sarkar (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A SPAD Based dToF Pixel with Log/Linear Multi-mode Operation for LiDAR Applications. - Sohail Faizan; Minal Bisen; Kapil Jainwal (ISCAS, 2023)

A 15-nW 14-ppm/°C 1.18 V startup-less bandgap-based voltage regulator. - Kapil Jainwal; Kalyan Kota Kumar; Gajendranath Chowdary; Shouri Chatterjee (ISCAS, 2023)

A Novel Active Pixel Sensor Architecture with In-Pixel Chopping and Switched Biasing to Reduce the Low-Frequency Noise. - Kapil Jainwal; Mukul Sarkar (ISCAS, 2023)

Design and Implementation of SPAD-Based Linearly Stable Multi-Mode Configurable TAC Pixel. - Minal Bisen; Kapil Jainwal; Nitin Khanna (VLSID, 2024)

Tau-Cell-Based Analog Silicon Retina With Spatio- Temporal Filtering and Contrast Gain Control. - Prince Philip; Kapil Jainwal; André van Schaik; Chetan Singh Thakur (IEEE Trans. Biomed. Circuits Syst., 2024)

Neuromorphic Retina: An FPGA-based Emulator. - Prince Phillip; Pallab Kumar Nath; Kapil Jainwal; André van Schaik; Chetan Singh Thakur (CoRR, 2025)