RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns. - Karam S. Chatha; Ranga Vemuri (CODES, 1998)

A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems. - Karam S. Chatha; Ranga Vemuri (ISSS, 1998)

Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns. - Karam S. Chatha; Ranga Vemuri (International Workshop on Rapid System Prototyping, 1998)

Hardware-Software Codesign for Dynamically Reconfigurable Architectures. - Karam S. Chatha; Ranga Vemuri (FPL, 1999)

An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems. - Karam S. Chatha; Ranga Vemuri (IEEE International Workshop on Rapid System Prototyping, 1999)

An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling. - Karam S. Chatha; Ranga Vemuri (Des. Autom. Embed. Syst., 2000)

MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs. - Karam S. Chatha; Ranga Vemuri (CODES, 2001)

Hardware-software partitioning and pipelined scheduling of transformative applications. - Karam S. Chatha; Ranga Vemuri (IEEE Trans. Very Large Scale Integr. Syst., 2002)

A Power and Performance Model for Network-on-Chip Architectures. - Nilanjan Banerjee; Praveen Vellanki; Karam S. Chatha (DATE, 2004)

Quality-of-service and error control techniques for network-on-chip architectures. - Praveen Vellanki; Nilanjan Banerjee; Karam S. Chatha (ACM Great Lakes Symposium on VLSI, 2004)

A Technique for Energy versus Quality of Service Trade-Off for MPEG-2 Decoder. - Krishnan Srinivasan; Vijay Ramamurthi; Karam S. Chatha (ISVLSI, 2004)

System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures. - Krishnan Srinivasan; Nagender Telkar; Vijay Ramamurthi; Karam S. Chatha (ISVLSI, 2004)

Efficient Stream Routing in Quality- and Resource-Adaptive Flow Architectures. - K. Selçuk Candan; Lina Peng; Kyung Dong Ryu; Karam S. Chatha; Christopher B. Mayer (Multimedia Information Systems, 2004)

ARIA: an adaptive and programmable media-flow architecture for interactive arts. - Lina Peng; K. Selçuk Candan; Kyung Dong Ryu; Karam S. Chatha; Hari Sundaram (ACM Multimedia, 2004)

An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures. - Krishnan Srinivasan; Karam S. Chatha (VLSI Design, 2004)

SAGA: synthesis technique for guaranteed throughput NoC architectures. - Krishnan Srinivasan; Karam S. Chatha (ASP-DAC, 2005)

An automated technique for topology and route generation of application specific on-chip interconnection networks. - Krishnan Srinivasan; Karam S. Chatha; Goran Konjevod (ICCAD, 2005)

A technique for low energy mapping and routing in network-on-chip architectures. - Krishnan Srinivasan; Karam S. Chatha (ISLPED, 2005)

System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures. - Vijaykumar Ramamurthi; Jason McCollum; Christopher Ostler; Karam S. Chatha (ISVLSI, 2005)

Media processing workflow design and execution with ARIA. - Lina Peng; Gisik Kwon; K. Selçuk Candan; Kyung Dong Ryu; Karam S. Chatha; Hari Sundaram; Yinpeng Chen (ACM Multimedia, 2005)

A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling. - Nagendran Rangan; Karam S. Chatha (VLSI Design, 2005)

ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis. - Krishnan Srinivasan; Karam S. Chatha (VLSI Design, 2005)

Quality-of-service and error control techniques for mesh-based network-on-chip architectures. - Praveen Vellanki; Nilanjan Banerjee; Karam S. Chatha (Integr., 2005)

Modular Design of Media Retrieval Workflows Using ARIA. - Lina Peng; Gisik Kwon; Yinpeng Chen; K. Selçuk Candan; Hari Sundaram; Karam S. Chatha; Maria Luisa Sapino (CIVR, 2006)

Layout aware design of mesh based NoC architectures. - Krishnan Srinivasan; Karam S. Chatha (CODES+ISSS, 2006)

A low complexity heuristic for design of custom network-on-chip architectures. - Krishnan Srinivasan; Karam S. Chatha (DATE, 2006)

A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures. - Krishnan Srinivasan; Karam S. Chatha (ISQED, 2006)

Linear-programming-based techniques for synthesis of network-on-chip architectures. - Krishnan Srinivasan; Karam S. Chatha; Goran Konjevod (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Approximation Algorithm for Process Mapping on Network Processor Architectures. - Christopher Ostler; Karam S. Chatha; Goran Konjevod (ASP-DAC, 2007)

Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms. - Krishnan Srinivasan; Karam S. Chatha; Goran Konjevod (ASP-DAC, 2007)

Smart driver for power reduction in next generation bistable electrophoretic display technology. - Michael A. Baker; Aviral Shrivastava; Karam S. Chatha (CODES+ISSS, 2007)

Performance and resource optimization of NoC router architecture for master and slave IP cores. - Glenn Leary; Krishna Mehta; Karam S. Chatha (CODES+ISSS, 2007)

Approximation Algorithm for Data Mapping on Block Multi-threaded Network Processor Architectures. - Christopher Ostler; Karam S. Chatha (DAC, 2007)

An ILP formulation for system-level application mapping on network processor architectures. - Christopher Ostler; Karam S. Chatha (DATE, 2007)

Approximation algorithm for the temperature-aware scheduling problem. - Sushu Zhang; Karam S. Chatha (ICCAD, 2007)

Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules. - Sushu Zhang; Karam S. Chatha; Goran Konjevod (ISLPED, 2007)

Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints. - Krishnan Srinivasan; Karam S. Chatha (Integr., 2007)

Optimization of media processing workflows with adaptive operator behaviors. - Lina Peng; K. Selçuk Candan; Christopher B. Mayer; Karam S. Chatha; Kyung Dong Ryu (Multim. Tools Appl., 2007)

ILP and heuristic techniques for system-level design on network processor architectures. - Christopher Ostler; Karam S. Chatha; Vijay Ramamurthi; Krishnan Srinivasan (ACM Trans. Design Autom. Electr. Syst., 2007)

Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures. - Sushu Zhang; Karam S. Chatha (ASP-DAC, 2008)

Power reduction via macroblock prioritization for power aware H.264 video applications. - Michael A. Baker; Viswesh Parameswaran; Karam S. Chatha; Baoxin Li (CODES+ISSS, 2008)

System-level thermal aware design of applications with uncertain execution time. - Sushu Zhang; Karam S. Chatha (ICCAD, 2008)

Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures. - Karam S. Chatha; Krishnan Srinivasan; Goran Konjevod (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A scalable parallel H.264 decoder on the cell broadband engine architecture. - Michael A. Baker; Pravin Dalale; Karam S. Chatha; Sarma B. K. Vrudhula (CODES+ISSS, 2009)

Automated technique for design of NoC with minimal communication latency. - Glenn Leary; Karam S. Chatha (CODES+ISSS, 2009)

Throughput optimal task allocation under thermal constraints for multi-core processors. - Vinay Hanumaiah; Ravishankar Rao; Sarma B. K. Vrudhula; Karam S. Chatha (DAC, 2009)

Performance optimal speed control of multi-core processors under thermal constraints. - Vinay Hanumaiah; Sarma B. K. Vrudhula; Karam S. Chatha (DATE, 2009)

Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. - Vinay Hanumaiah; Sarma B. K. Vrudhula; Karam S. Chatha (ICCAD, 2009)

Near optimal battery-aware energy management. - Sushu Zhang; Karam S. Chatha; Goran Konjevod (ISLPED, 2009)

Circuits and systems for real-time security and copyright protection of multimedia. - Saraju P. Mohanty; Nasir D. Memon; Karam S. Chatha (Comput. Electr. Eng., 2009)

Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique. - Glenn Leary; Krishnan Srinivasan; Krishna Mehta; Karam S. Chatha (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Design of an Automatic Target Recognition algorithm on the IBM Cell Broadband Engine. - Weijia Che; Karam S. Chatha (ASAP, 2010)

A performance model and code overlay generator for scratchpad enhanced embedded processors. - Michael A. Baker; Amrit Panda; Nikhil Ghadge; Aniruddha Kadne; Karam S. Chatha (CODES+ISSS, 2010)

A holistic approach to network-on-chip synthesis. - Glenn Leary; Karam S. Chatha (CODES+ISSS, 2010)

Thermal aware task sequencing on embedded processors. - Sushu Zhang; Karam S. Chatha (DAC, 2010)

Compilation of stream programs for multicore processors that incorporate scratchpad memories. - Weijia Che; Amrit Panda; Karam S. Chatha (DATE, 2010)

Scheduling of synchronous data flow models on scratchpad memory based embedded processors. - Weijia Che; Karam S. Chatha (ICCAD, 2010)

A lightweight run-time scheduler for multitasking multicore stream applications. - Michael A. Baker; Karam S. Chatha (ICCD, 2010)

Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance. - Glenn Leary; Karam S. Chatha (VLSI Design, 2010)

Compilation of stream programs onto scratchpad memory based embedded multicore processors through retiming. - Weijia Che; Karam S. Chatha (DAC, 2011)

Scheduling of stream programs onto SPM enhanced processors with code overlay. - Weijia Che; Karam S. Chatha (ESTIMedia, 2011)

Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors. - Vinay Hanumaiah; Sarma B. K. Vrudhula; Karam S. Chatha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Dynamic scheduling of stream programs on embedded multi-core processors. - Haeseung Lee; Weijia Che; Karam S. Chatha (CODES+ISSS, 2012)

Unrolling and retiming of stream applications onto embedded multicore processors. - Weijia Che; Karam S. Chatha (DAC, 2012)

System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC. - Glenn Leary; Weijia Che; Karam S. Chatha (DAC, 2012)

Scheduling of synchronous data flow models onto scratchpad memory-based embedded processors. - Weijia Che; Karam S. Chatha (ACM Trans. Embed. Comput. Syst., 2013)

An embedded co-processor architecture for energy-efficient stream computing. - Amrit Panda; Karam S. Chatha (ESTIMedia, 2014)

An Embedded Architecture for Energy-Efficient Stream Computing. - Amrit Panda; Karam S. Chatha (IEEE Embed. Syst. Lett., 2014)

Guest Editors' Introduction - Special Issue on Network-on-Chip. - Ran Ginosar; Karam S. Chatha (IEEE Trans. Computers, 2014)