An algorithm for exploiting modeling error statistics to enable robust analog optimization. - Ashish Kumar Singh; Mario Lok; Kareem Ragab; Constantine Caramanis; Michael Orshansky (ICCAD, 2010)

Embracing local variability to enable a robust high-gain positive-feedback amplifier: Design methodology and implementation. - Kareem Ragab; Ranjit Gharpurey; Michael Orshansky (ISQED, 2012)

Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics. - Ashish Kumar Singh; Kareem Ragab; Mario Lok; Constantine Caramanis; Michael Orshansky (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Thermal Noise Analysis of a Programmable-Gain Switched-Capacitor Amplifier With Input Offset Cancellation. - Kareem Ragab; Mücahit Kozak; Nan Sun 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping. - Arindam Sanyal; Kareem Ragab; Long Chen 004; T. R. Viswanathan 001; Shouli Yan; Nan Sun 001 (CICC, 2014)

A 12b ENOB, 2.5MHz-BW, 4.8mW VCO-based 0-1 MASH ADC with direct digital background nonlinearity calibration. - Kareem Ragab; Nan Sun 001 (CICC, 2015)

Digital Background Calibration for Pipelined ADCs Based on Comparator Decision Time Quantization. - Kareem Ragab; Long Chen 004; Arindam Sanyal; Nan Sun 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A 10-b 800MS/s time-interleaved SAR ADC with fast timing-skew calibration. - Jeonggoo Song; Kareem Ragab; Xiyuan Tang; Nan Sun 001 (A-SSCC, 2016)

A 1.4mW 8b 350MS/s loop-unrolled SAR ADC with background offset calibration in 40nm CMOS. - Kareem Ragab; Nan Sun 001 (ESSCIRC, 2016)

A 12-b ENOB 2.5-MHz BW VCO-Based 0-1 MASH ADC With Direct Digital Background Calibration. - Kareem Ragab; Nan Sun 001 (IEEE J. Solid State Circuits, 2017)

A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration. - Jeonggoo Song; Kareem Ragab; Xiyuan Tang; Nan Sun 001 (IEEE J. Solid State Circuits, 2017)

A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS. - Long Chen 004; Kareem Ragab; Xiyuan Tang; Jeonggoo Song; Arindam Sanyal; Nan Sun 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs. - Shaolan Li; Arindam Sanyal; Kyoungtae Lee; Yeonam Yoon; Xiyuan Tang; Yi Zhong; Kareem Ragab; Nan Sun 001 (IEICE Trans. Electron., 2019)

A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration. - Jeonggoo Song; Kareem Ragab; Xiyuan Tang; Nan Sun 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Fast Converging Correlation-Based Background Timing Skew Calibration Technique by Digital Windowing for Time-Interleaved ADCs. - Yunsong Tao; Kareem Ragab; Jin Shao; Pengpeng Chen; Yi Zhong; Lu Jie 001; Nan Sun 001 (ISCAS, 2022)

Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques. - Xiyuan Tang; Jiaxin Liu; Yi Shen 007; Shaolan Li; Linxiao Shen; Arindam Sanyal; Kareem Ragab; Nan Sun 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)