Programmable Dictionary Code Compression for Instruction Stream Energy Efficiency. - Joonas Multanen; Kari Hepola; Pekka Jääskeläinen (ICCD, 2020)

Dual-IS: Instruction Set Modality for Efficient Instruction Level Parallelism. - Kari Hepola; Joonas Multanen; Pekka Jääskeläinen (ARCS, 2022)

OpenASIP 2.0: Co-Design Toolset for RISC-V Application-Specific Instruction-Set Processors. - Kari Hepola; Joonas Multanen; Pekka Jääskeläinen (ASAP, 2022)

Energy-Efficient Instruction Delivery in Embedded Systems With Domain Wall Memory. - Joonas Multanen; Kari Hepola; Asif Ali Khan; Jerónimo Castrillón; Pekka Jääskeläinen (IEEE Trans. Computers, 2022)

AEx: Automated High-Level Synthesis of Compiler Programmable Co-Processors. - Alex Hirvonen; Topi Leppänen; Kari Hepola; Joonas Multanen; Joost Hoozemans; Pekka Jääskeläinen (J. Signal Process. Syst., 2023)

Fully Automatic Compiler Retargeting and CV-X-IF Hardware Interface Generation for RISC-V Custom Instructions. - Kari Hepola; Tharaka Ranasinghe Arachchige; Joonas Multanen; Pekka Jääskeläinen (NorCAS, 2024)

Cycle Count Estimation of VLIW Processors Using Machine Learning. - Kari Hepola; Jatan Shrestha; Joonas Multanen; Vivienne Wang; Joni Pajarinen; Pekka Jääskeläinen (NorCAS, 2024)

Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode. - Kari Hepola; Joonas Multanen; Pekka Jääskeläinen (IEEE Trans. Computers, 2024)