A generic pixel distribution architecture for parallel video processing. - Karim M. A. Ali; Rabie Ben Atitallah; Saïd Hanafi; Jean-Luc Dekeyser (ReConFig, 2014)

Using hardware parallelism for reducing power consumption in video streaming applications. - Karim M. A. Ali; Rabie Ben Atitallah; Nizar Fakhfakh; Jean-Luc Dekeyser (ReCoSoC, 2015)

Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation. - Karim M. A. Ali; Rabie Ben Atitallah; Nizar Fakhfakh; Jean-Luc Dekeyser (ARC, 2017)

FPGA-Centric High Performance Embedded Computing: Challenges and Trends. - Rabie Ben Atitallah; Karim M. A. Ali (DSD, 2017)

An Efficient Hardware Implementation of TimSort and MergeSort Algorithms Using High Level Synthesis. - Yomna Ben Jmaa; Karim M. A. Ali; David Duvivier; Maher Ben Jemaa; Rabie Ben Atitallah (HPCS, 2017)

An Embedded Multi-Sensor Data Fusion Design for Vehicle Perception Tasks. - Mokhtar Bouain; Karim M. A. Ali; Denis Berdjag; Nizar Fakhfakh; Rabie Ben Atitallah (J. Commun., 2018)

ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures. - Karim M. A. Ali; Rabie Ben Atitallah; Abdessamad Ait El Cadi; Nizar Fakhfakh; Jean-Luc Dekeyser (Int. J. Reconfigurable Comput., 2019)

Case study of an HEVC decoder application using high-level synthesis: intraprediction, dequantization, and inverse transform blocks. - Manel Kammoun; Ahmed Ben Atitallah; Karim M. A. Ali; Rabie Ben Atitallah (J. Electronic Imaging, 2019)

Cross-layer CNN Approximations for Hardware Implementation. - Karim M. A. Ali; Ihsen Alouani; Abdessamad Ait El Cadi; Hamza Ouarnoughi; Smaïl Niar (ARC, 2020)

An FPGA comparative study of high-level and low-level combined designs for HEVC intra, inverse quantization, and IDCT/IDST 2D modules. - Ahmed Ben Atitallah; Manel Kammoun; Karim M. A. Ali; Rabie Ben Atitallah (Int. J. Circuit Theory Appl., 2020)