Designing the MPC105 PCI bridge/memory controller. - Karl Wang; Christopher D. Bryant; Mike Carlson; Tom Elmer; Adrian Harris; Michael J. Garcia; C. S. Hui; C. K. Leung; Brian K. Reynolds; Raymond Tang; Laura A. Weber; Jim Wenzel; et al. (IEEE Micro, 1995)

Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell. - Kenichi Osada; Jinuk Luke Shin; Masood Khan; Yude Liou; Karl Wang; Kenichi Shoji; Kenichi Kuroda; Shuji Ikeda; Koichiro Ishibashi (IEEE J. Solid State Circuits, 2001)