According to our database1, Karthik Chandrasekar authored at least 12 papers between 2007 and 2016.
Legend:Book In proceedings Article PhD thesis Other
Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling.
IEEE Trans. Computers, 2016
Exploiting expendable process-margins in DRAMs for run-time performance optimization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Virtual execution platforms for mixed-time-criticality systems: the CompSOC architecture and design flow.
SIGBED Rev., 2013
TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration.
Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2013
System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs.
Proceedings of the Design, Automation and Test in Europe, 2013
Towards variation-aware system-level power estimation of DRAMs: an empirical approach.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
A Predictor-Based Power-Saving Policy for DRAM Memories.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Run-time power-down strategies for real-time SDRAM memory controllers.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Improved Power Modeling of DDR SDRAMs.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Design for Testability of Functional Cores in High Performance Node Architectures.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
Future generation supercomputers I: a paradigm for node architecture.
SIGARCH Computer Architecture News, 2007