Future generation supercomputers I: a paradigm for node architecture. - Nagarajan Venkateswaran; Deepak Srinivasan; Madhavan Manivannan; T. P. Ramnath Sai Sagar; Shyamsundar Gopalakrishnan; Vinoth Krishnan Elangovan; Karthik Chandrasekar 001; Prem Kumar Ramesh; Viswanath Venkatesan; Arvindakshan Babu; Sudharshan (SIGARCH Comput. Archit. News, 2007)

Design for Testability of Functional Cores in High Performance Node Architectures. - Nagarajan Venkateswaran; Karthik Chandrasekar 001; Shrikanth Ganapathy (DELTA, 2008)

On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system. - N. Venkateswaran 002; Vinoth Krishnan Elangovan; Karthik Ganesan 006; TP Ramnath Sai Sagar; Sriram Aananthakrishanan; Shreyas Ramalingam; Shyamsundar Gopalakrishnan; Madhavan Manivannan; Deepak Srinivasan; Viswanath Krishnamurthy; Karthik Chandrasekar 001; Viswanath Venkatesan; et al. (IPDPS, 2008)

Improved Power Modeling of DDR SDRAMs. - Karthik Chandrasekar 001; Benny Akesson; Kees Goossens (DSD, 2011)

Run-time power-down strategies for real-time SDRAM memory controllers. - Karthik Chandrasekar 001; Benny Akesson; Kees Goossens (DAC, 2012)

A Predictor-Based Power-Saving Policy for DRAM Memories. - Gervin Thomas; Karthik Chandrasekar 001; Benny Akesson; Ben H. H. Juurlink; Kees Goossens (DSD, 2012)

Towards variation-aware system-level power estimation of DRAMs: an empirical approach. - Karthik Chandrasekar 001; Christian Weis; Benny Akesson; Norbert Wehn; Kees Goossens (DAC, 2013)

System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs. - Karthik Chandrasekar 001; Christian Weis; Benny Akesson; Norbert Wehn; Kees Goossens (DATE, 2013)

TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration. - Matthias Jung 001; Christian Weis; Norbert Wehn; Karthik Chandrasekar 001 (RAPIDO, 2013)

Virtual execution platforms for mixed-time-criticality systems: the CompSOC architecture and design flow. - Kees Goossens; Arnaldo Azevedo; Karthik Chandrasekar 001; Manil Dev Gomony; Sven Goossens; Martijn Koedam; Yonghui Li 002; Davit Mirzoyan; Anca Mariana Molnos; Ashkan Beyranvand Nejad; Andrew Nelson 001; Shubhendu Sinha (SIGBED Rev., 2013)

Exploiting expendable process-margins in DRAMs for run-time performance optimization. - Karthik Chandrasekar 001; Sven Goossens; Christian Weis; Martijn Koedam; Benny Akesson; Norbert Wehn; Kees Goossens (DATE, 2014)

Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling. - Sven Goossens; Karthik Chandrasekar 001; Benny Akesson; Kees Goossens (IEEE Trans. Computers, 2016)