Determination of worst-case aggressor alignment for delay calculation. - Paul D. Gross; Ravishankar Arunachalam; Karthik Rajagopal; Lawrence T. Pileggi (ICCAD, 1998)

TACO: timing analysis with coupling. - Ravishankar Arunachalam; Karthik Rajagopal; Lawrence T. Pileggi (DAC, 2000)

Force directed mongrel with physical net constraints. - Sung-Woo Hur; Tung Cao; Karthik Rajagopal; Yegna Parasuram; Amit Chowdhary; Vladimir Tiourin; Bill Halpin (DAC, 2003)

Timing driven force directed placement with physical net constraints. - Karthik Rajagopal; Tal Shaked; Yegna Parasuram; Tung Cao; Amit Chowdhary; Bill Halpin (ISPD, 2003)

A high performance, high voltage output buffer in a low voltage CMOS process. - Rajat Chauhan; Karthik Rajagopal; Vinod Menezes; H. M. Roopashree; Sanish Koshy Jacob (CICC, 2005)

How accurately can we model timing in a placement engine? - Amit Chowdhary; Karthik Rajagopal; Satish Venkatesan; Tung Cao; Vladimir Tiourin; Yegna Parasuram; Bill Halpin (DAC, 2005)

An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage process. - Karthik Rajagopal; Aatmesh; Vinod Menezes (ISQED, 2009)

Designing better strategies against human adversaries in network security games. - Rong Yang 001; Fei Fang 001; Albert Xin Jiang; Karthik Rajagopal; Milind Tambe; Rajiv T. Maheswaran (AAMAS, 2012)

Dynamically biased low power high performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm process. - Karthik Rajagopal (ISQED, 2012)