Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. - Sanjukta Bhanja; Karthikeyan Lingasubramanian; N. Ranganathan (VLSI Design, 2005)

A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. - Sanjukta Bhanja; Karthikeyan Lingasubramanian; N. Ranganathan (ACM Trans. Design Autom. Electr. Syst., 2006)

Probabilistic maximum error modeling for unreliable logic circuits. - Karthikeyan Lingasubramanian; Sanjukta Bhanja (ACM Great Lakes Symposium on VLSI, 2007)

An Error Model to Study the Behavior of Transient Errors in Sequential Circuits. - Karthikeyan Lingasubramanian; Sanjukta Bhanja (VLSI Design, 2009)

Study of Circuit-Specific Error Bounds for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis - Karthikeyan Lingasubramanian; Syed M. Alam; Sanjukta Bhanja (CoRR, 2009)

Probabilistic Error Modeling for Nano-Domain Logic Circuits. - Thara Rejimon; Karthikeyan Lingasubramanian; Sanjukta Bhanja (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. - Karthikeyan Lingasubramanian; Andrea Calimera; Alberto Macii; Enrico Macii; Massimo Poncino (PATMOS, 2011)

Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis. - Karthikeyan Lingasubramanian; Syed M. Alam; Sanjukta Bhanja (Microelectron. Reliab., 2011)

Realizing a security aware triple modular redundancy scheme for robust integrated circuits. - Gunti Nagendra Babu; Aman Khatri; Karthikeyan Lingasubramanian (VLSI-SoC, 2014)

Neutralization of the Effect of Hardware Trojan in SCADA System Using Selectively Placed TMR. - Nagendra Babu Gunti; Karthikeyan Lingasubramanian (iNIS, 2017)

Fault Sensitive Neutralization of Hardware Trojans Using Multi-level Triple Modular Redundancy Scheme. - Nagendra Babu Gunti; Karthikeyan Lingasubramanian (iNIS, 2017)

Effective usage of redundancy to aid neutralization of hardware Trojans in Integrated Circuits. - Gunti Nagendra Babu; Karthikeyan Lingasubramanian (Integr., 2017)

Effect of hardware Trojans on the performance of a coded communication system. - A. R. Aravind; S. R. Kesavaraman; Karthi Balasubramanian; B. Yamuna; Karthikeyan Lingasubramanian (ICCE, 2018)

Study of hardware trojans based security vulnerabilities in cyber physical systems. - Karthikeyan Lingasubramanian; Ranveer Kumar; Nagendra Babu Gunti; Thomas H. Morris (ICCE, 2018)

Effect of sign-bit-flipping trojan on turbo coded communication systems. - Karthi Balasubramanian; B. Yamuna; Salija P; Karthikeyan Lingasubramanian; Deepak Mishra (ICDCN, 2019)

A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study. - Varsha Kakkara; Karthi Balasubramanian; B. Yamuna; Deepak Mishra; Karthikeyan Lingasubramanian; Senthil Murugan (PeerJ Comput. Sci., 2020)