Chameleon: a new multi-layer channel router. - Douglas Braun; Jeffrey L. Burns; Srinivas Devadas; Hi-Keung Tony Ma; Kartikeya Mayaram; Fabio Romeo; Alberto L. Sangiovanni-Vincentelli (DAC, 1986)

CODECS: a fixed mixed-level device and circuit simulator. - Kartikeya Mayaram; Donald O. Pederson (ICCAD, 1988)

Techniques for multilayer channel routing. - Douglas Braun; Jeffrey L. Burns; Fabio Romeo; Alberto L. Sangiovanni-Vincentelli; Kartikeya Mayaram; Srinivas Devadas; Hi-Keung Tony Ma (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

PGS and PLUCGS-two new matrix solution techniques for general circuit simulation. - Richard Burch; Kartikeya Mayaram; Jue-Hsien Chern; Ping Yang 001; Paul F. Cox (ICCAD, 1989)

Analog integrated circuits for communication - principles, simulation and design. - Donald O. Pederson; Kartikeya Mayaram (Kluwer, 1990)

A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit and Device Simulations. - Kartikeya Mayaram; Ping Yang 001; Jue-Hsien Chern; Richard Burch; Lawrence A. Arledge Jr.; Paul F. Cox (ICCAD, 1990)

Transient Three-Dimensional Mixed-Level Circuit and Device Simulation: Algorithms and Applications. - Kartikeya Mayaram; Ping Yang 001; Jue-Hsien Chern (ICCAD, 1991)

Coupling algorithms for mixed-level circuit and device simulation. - Kartikeya Mayaram; Donald O. Pederson (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

A new matrix solution technique for general circuit simulation. - Richard Burch; Ping Yang 001; Paul F. Cox; Kartikeya Mayaram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Algorithms for transient three-dimensional mixed-level circuit and device simulation. - Kartikeya Mayaram; Jue-Hsien Chern; Ping Yang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Comments on "A small-signal MOSFET model for radio frequency IC applications". - Suet Fong Tin; Ashraf A. Osman; Kartikeya Mayaram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Substrate network modeling for CMOS RF circuit simulation. - Suet Fong Tin; Kartikeya Mayaram (CICC, 1999)

A scalable substrate noise coupling model for mixed-signal ICs. - Anil Samavedam; Kartikeya Mayaram; Terri S. Fiez (ICCAD, 1999)

Design-oriented substrate noise coupling macromodels for heavily doped CMOS processes. - Anil Samavedam; Kartikeya Mayaram; Terri S. Fiez (ISCAS (6), 1999)

Neural Network Design for Behavioral Model Generation with Shape Preserving Properties. - Oleg Mikulchenko; Kartikeya Mayaram (BMAS, 2000)

A scalable substrate noise coupling model for design of mixed-signal IC's. - Anil Samavedam; Aline Sadate; Kartikeya Mayaram; Terri S. Fiez (IEEE J. Solid State Circuits, 2000)

A simple subcircuit extension of the BSIM3v3 model for CMOS RF design. - Suet Fong Tin; Ashraf A. Osman; Kartikeya Mayaram; Chenming Hu (IEEE J. Solid State Circuits, 2000)

A simple and accurate method for calculating the low frequency common-mode gain in a MOS differential amplifier with a current-mirror load. - Ruoxin Jiang; Haiming Tang; Kartikeya Mayaram (IEEE Trans. Educ., 2000)

The effect of supply and substrate noise on jitter in ring oscillators. - Nathen Barton; Dicle Ozis; Terri S. Fiez; Kartikeya Mayaram (CICC, 2002)

A comprehensive geometry-dependent macromodel for substrate noise coupling in heavily doped CMOS processes. - Dicle Ozis; Terri S. Fiez; Kartikeya Mayaram (CICC, 2002)

Analysis of jitter in ring oscillators due to deterministic noise. - Nathen Barton; Dicle Özis; Terri S. Fiez; Kartikeya Mayaram (ISCAS (4), 2002)

Analysis of CMOS RF LNAs with ESD protection. - V. Chandrasekhar; Kartikeya Mayaram (ISCAS (4), 2002)

An efficient algorithm for large-signal frequency-domain coupled device and circuit simulation [RF circuits]. - Yutao Hu 001; Kartikeya Mayaram (ISCAS (5), 2002)

HomSSPICE: a homotopy-based circuit simulator for periodic steady-state analysis of oscillators. - Wanliang Ma; Ljiljana Trajkovic; Kartikeya Mayaram (ISCAS (1), 2002)

An efficient modeling approach for substrate noise coupling analysis. - Dicle Ozis; Kartikeya Mayaram; Terri S. Fiez (ISCAS (5), 2002)

Design of low power 2.4 GHz CMOS LC oscillators with low phase-noise and large tuning range. - N. Seshan; J. Rajagopalan; Kartikeya Mayaram (ISCAS (4), 2002)

A comparison of non-quasi-static and quasi-static harmonic balance implementations for coupled device and circuit simulation. - Yutao Hu 001; Kartikeya Mayaram (CICC, 2003)

Piezoelectric power generation interface circuits. - Triet Le; Jifeng Han; Annette R. von Jouanne; Kartikeya Mayaram; Terri S. Fiez (CICC, 2003)

Strategies for simulation, measurement and suppression of digital noise in mixed-signal circuits. - Brian E. Owens; Patrick Birrer; Sirisha Adluri; Robert Shreeve; Sasi Kumar Arunachalam; Husni Habal; Shu-Ching Hsu; Ajit Sharma; Kartikeya Mayaram; Terri S. Fiez (CICC, 2003)

Symbolic Analysis of Nonlinear Analog Circuits. - Alicia Manthe; Zhao Li; Chuanjin Richard Shi; Kartikeya Mayaram (DATE, 2003)

Coupled Simulation of Circuit and Piezoelectric Laminates. - Chenggang Xu; Terri S. Fiez; Kartikeya Mayaram (ISQED, 2003)

CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects. - Zhao Li; Ravikanth Suravarapu; Roy Hartono; Sambuddha Bhattacharya; Kartikeya Mayaram; Chuanjin Richard Shi (ASP-DAC, 2004)

Digital noise coupling mechanisms in a 2.4 GHz LNA for heavily and lightly doped CMOS substrates. - Scott Hazenboom; Terri S. Fiez; Kartikeya Mayaram (CICC, 2004)

A modified-Volterra-series technique for improving the accuracy of quasi-static harmonic balance analysis in coupled device and circuit simulation. - Yutao Hu 001; Kartikeya Mayaram (CICC, 2004)

Frequency domain simulation of high-Q oscillators with homotopy methods. - Xiaochun Duan; Kartikeya Mayaram (ICCAD, 2004)

Accurate simulation of phase noise in RF MEMS VCOs. - Manas Behera; Volodymyr Kratyuk; Yutao Hu 001; Kartikeya Mayaram (ISCAS (3), 2004)

An accurate and efficient estimation of switching noise in synchronous digital circuits. - Husni M. Habal; Terri S. Fiez; Kartikeya Mayaram (ISCAS (2), 2004)

A predictive methodology for accurate substrate parasitic extraction. - Ajit Sharma; Chenggang Xu; Wen Kung Chu; Nishath K. Verghese; Terri S. Fiez; Kartikeya Mayaram (ISCAS (5), 2004)

A physical and analytical model for substrate noise coupling analysis. - Robert Shreeve; Terri S. Fiez; Kartikeya Mayaram (ISCAS (5), 2004)

An improved Z-parameter macro model for substrate noise coupling. - Chenggang Xu; Terri S. Fiez; Kartikeya Mayaram (ISCAS (5), 2004)

Silencer!: a tool for substrate noise coupling analysis. - Patrick Birrer; Terri S. Fiez; Kartikeya Mayaram (SoCC, 2004)

Analysis of charge-pump phase-locked loops. - Pavan Kumar Hanumolu; Merrick Brownlee; Kartikeya Mayaram; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

An efficient formulation for substrate parasitic extraction accounting for nonuniform current distribution. - Chenggang Xu; Terri S. Fiez; Kartikeya Mayaram (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

A new approach for ring oscillator simulation using the harmonic balance method. - Xiaochun Duan; Kartikeya Mayaram (ASP-DAC, 2005)

A multiple-probe approach for robust frequency domain ring oscillator simulation. - Xiaochun Duan; Kartikeya Mayaram (CICC, 2005)

A green function-based parasitic extraction method for inhomogeneous substrate layers. - Chenggang Xu; Ranjit Gharpurey; Terri S. Fiez; Kartikeya Mayaram (DAC, 2005)

A low spur fractional-N frequency synthesizer architecture. - Volodymyr Kratyuk; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (ISCAS (3), 2005)

Analysis of supply and ground noise sensitivity in ring and LC oscillators. - Volodymyr Kratyuk; Igor Vytyaz; Un-Ku Moon; Kartikeya Mayaram (ISCAS (6), 2005)

An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications. - Ting Wu 003; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (ISCAS (4), 2005)

Simulation and measurement of supply and substrate noise in mixed-signal ICs. - Brian E. Owens; Sirisha Adluri; Patrick Birrer; Robert Shreeve; Sasi Kumar Arunachalam; Kartikeya Mayaram; Terri S. Fiez (IEEE J. Solid State Circuits, 2005)

An efficient and robust method for ring-oscillator simulation using the harmonic-balance method. - Xiaochun Duan; Kartikeya Mayaram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

On the numerical stability of Green's function for substrate coupling in integrated circuits. - Chenggang Xu; Terri S. Fiez; Kartikeya Mayaram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Accurate and efficient simulation of synchronous digital switching noise in systems on a chip. - Husni M. Habal; Kartikeya Mayaram; Terri S. Fiez (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver. - Ajit Sharma; Patrick Birrer; Sasi Kumar Arunachalam; Chenggang Xu; Terri S. Fiez; Kartikeya Mayaram (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry. - Jim Le; Christopher Hanken; Martin Held; Michael S. Hagedorn; Kartikeya Mayaram; Terri S. Fiez (CICC, 2006)

Efficient Far-Field Radio Frequency Power Conversion System for Passively Powered Sensor Networks. - Triet Le; Kartikeya Mayaram; Terri S. Fiez (CICC, 2006)

Sizing Ground Taps to Minimize Substrate Noise Coupling in RF LNAs. - Arathi Sundaresan; Terri S. Fiez; Kartikeya Mayaram (CICC, 2006)

Dependence of LC VCO oscillation frequency on bias current. - Ting Wu 003; Un-Ku Moon; Kartikeya Mayaram (ISCAS, 2006)

A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning. - Merrick Brownlee; Pavan Kumar Hanumolu; Kartikeya Mayaram; Un-Ku Moon (ISSCC, 2006)

CEDA Currents. - Kartikeya Mayaram (IEEE Des. Test Comput., 2006)

A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning. - Merrick Brownlee; Pavan Kumar Hanumolu; Kartikeya Mayaram; Un-Ku Moon (IEEE J. Solid State Circuits, 2006)

A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4-GHz LNAs. - Scott Hazenboom; Terri S. Fiez; Kartikeya Mayaram (IEEE J. Solid State Circuits, 2006)

Piezoelectric micro-power generation interface circuits. - Triet Le; Jifeng Han; Annette R. von Jouanne; Kartikeya Mayaram; Terri S. Fiez (IEEE J. Solid State Circuits, 2006)

Frequency-Domain Simulation of Ring Oscillators With a Multiple-Probe Method. - Xiaochun Duan; Kartikeya Mayaram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Robust Simulation of High-Q Oscillators Using a Homotopy-Based Harmonic Balance Method. - Xiaochun Duan; Kartikeya Mayaram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Comparison of Algorithms for Frequency Domain Coupled Device and Circuit Simulation. - Yutao Hu 001; Kartikeya Mayaram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs. - Chenggang Xu; Terri S. Fiez; Kartikeya Mayaram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs. - Patrick Birrer; Sasi Kumar Arunachalam; Martin Held; Kartikeya Mayaram; Terri S. Fiez (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic Circuits. - Christopher Hanken; Jim Le; Terri S. Fiez; Kartikeya Mayaram (CICC, 2007)

Digitally-Enhanced Phase-Locking Circuits. - Pavan Kumar Hanumolu; Gu-Yeon Wei; Un-Ku Moon; Kartikeya Mayaram (CICC, 2007)

A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range. - Volodymyr Kratyuk; Pavan Kumar Hanumolu; Kartikeya Mayaram; Un-Ku Moon (CICC, 2007)

Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates. - Brett Peterson; Kartikeya Mayaram; Terri S. Fiez (CICC, 2007)

A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop. - Ting Wu 003; Pavan Kumar Hanumolu; Kartikeya Mayaram; Un-Ku Moon (CICC, 2007)

Parameter Finding Methods for Oscillators with a Specified Oscillation Frequency. - Igor Vytyaz; David C. Lee; Suihua Lu; Amit Mehrotra; Un-Ku Moon; Kartikeya Mayaram (DAC, 2007)

Design and Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells. - Josh Carnes; Igor Vytyaz; Pavan Kumar Hanumolu; Kartikeya Mayaram; Un-Ku Moon (ICECS, 2007)

Tradeoffs in the Design of CMOS Receivers for Low Power Wireless Sensor Networks. - James Ayers; Kartikeya Mayaram; Terri S. Fiez (ISCAS, 2007)

A Low Power BFSK Super-Regenerative Transceiver. - James Ayers; Kartikeya Mayaram; Terri S. Fiez (ISCAS, 2007)

Design of Very Low Noise 4.2GHz Clapp VCOs. - Raghuram Jonnalagedda; Kartikeya Mayaram (ISCAS, 2007)

Noise Simulation and Modeling for MEMS Varactor Based RF VCOs. - Janakiram G. Sankaranarayanan; Kartikeya Mayaram (ISCAS, 2007)

Periodic Steady-State Analysis of Oscillators with a Specified Oscillation Frequency. - Igor Vytyaz; David C. Lee; Suihua Lu; Amit Mehrotra; Un-Ku Moon; Kartikeya Mayaram (ISCAS, 2007)

Issues in the Design and Simulation of a MEMS VCO based Phase-Locked Loop. - Maneesha Yellepeddi; Kartikeya Mayaram (ISCAS, 2007)

An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators. - Ting Wu 003; Kartikeya Mayaram; Un-Ku Moon (IEEE J. Solid State Circuits, 2007)

A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy. - Volodymyr Kratyuk; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A 0.4 nJ/b 900MHz CMOS BFSK super-regenerative receiver. - James Ayers; Kartikeya Mayaram; Terri S. Fiez (CICC, 2008)

A 900-MHz low-power transmitter with fast frequency calibration for wireless sensor networks. - Napong Panitantum; Kartikeya Mayaram; Terri S. Fiez (CICC, 2008)

Noise tolerant oscillator design using perturbation projection vector analysis. - Igor Vytyaz; Josh Carnes; Ting Wu 003; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (CICC, 2008)

Periodic Steady-State Analysis Augmented with Design Equality Constraints. - Igor Vytyaz; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (DATE, 2008)

Parameter variation analysis for voltage controlled oscillators in phase-locked loops. - Igor Vytyaz; David C. Lee; Un-Ku Moon; Kartikeya Mayaram (ISCAS, 2008)

Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks. - Triet Le; Kartikeya Mayaram; Terri S. Fiez (IEEE J. Solid State Circuits, 2008)

Sensitivity Analysis for Oscillators. - Igor Vytyaz; David C. Lee; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method. - Chenggang Xu; Ranjit Gharpurey; Terri S. Fiez; Kartikeya Mayaram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processes. - Wai Leng Cheong; Brian E. Owens; Hui En Pham; Christopher Hanken; Jim Le; Terri S. Fiez; Kartikeya Mayaram (ISQED, 2009)

Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers. - Ting Wu 003; Pavan Kumar Hanumolu; Kartikeya Mayaram; Un-Ku Moon (IEEE J. Solid State Circuits, 2009)

Automated Design and Optimization of Low-Noise Oscillators. - Igor Vytyaz; David C. Lee; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

A Digital PLL With a Stochastic Time-to-Digital Converter. - Volodymyr Kratyuk; Pavan Kumar Hanumolu; Kerem Ok; Un-Ku Moon; Kartikeya Mayaram (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A 475 mV, 4.9 GHz enhanced swing differential Colpitts VCO in 130 nm CMOS with an FoM of 196.2 dBc/Hz. - Farhad Farhabakhshian; Thomas William Brown; Kartikeya Mayaram; Terri S. Fiez (CICC, 2010)

An Ultralow-Power Receiver for Wireless Sensor Networks. - James Ayers; Kartikeya Mayaram; Terri S. Fiez (IEEE J. Solid State Circuits, 2010)

A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. - Samira Zali Asl; Saurabh Saxena; Pavan Kumar Hanumolu; Kartikeya Mayaram; Terri S. Fiez (CICC, 2011)

A 475 mV, 4.9 GHz Enhanced Swing Differential Colpitts VCO With Phase Noise of -136 dBc/Hz at a 3 MHz Offset Frequency. - Thomas William Brown; Farhad Farhabakhshian; Ankur Guha Roy; Terri S. Fiez; Kartikeya Mayaram (IEEE J. Solid State Circuits, 2011)

A 250 mV, 352 μ W GPS Receiver RF Front-End in 130 nm CMOS. - Adam C. Heiberg; Thomas William Brown; Terri S. Fiez; Kartikeya Mayaram (IEEE J. Solid State Circuits, 2011)

A Multiple-Input Boost Converter for Low-Power Energy Harvesting. - Chao Shi; Brian Miller; Kartikeya Mayaram; Terri S. Fiez (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Design-Oriented Analysis of Circuits With Equality Constraints. - Igor Vytyaz; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A 2.4GHz hybrid PPF based BFSK receiver with ±180ppm frequency offset tolerance for wireless sensor networks. - Ronghua Ni; Kartikeya Mayaram; Terri S. Fiez (VLSIC, 2012)

A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC. - Samira Zali Asl; Saurabh Saxena; Pavan Kumar Hanumolu; Kartikeya Mayaram; Terri S. Fiez (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry. - Jim Le; Christopher Hanken; Martin Held; Michael S. Hagedorn; Kartikeya Mayaram; Terri S. Fiez (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks. - Ronghua Ni; Kartikeya Mayaram; Terri S. Fiez (IEEE J. Solid State Circuits, 2013)

A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM. - Ankur Guha Roy; Siladitya Dey 002; Justin B. Goins; Kartikeya Mayaram; Terri S. Fiez (CICC, 2014)

A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with -76dBm sensitivity for high data rate wireless sensor networks. - Ronghua Ni; Kartikeya Mayaram; Terri S. Fiez (VLSIC, 2014)

350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS. - Ankur Guha Roy; Siladitya Dey 002; Justin B. Goins; Terri S. Fiez; Kartikeya Mayaram (IEEE J. Solid State Circuits, 2015)

JetNet: A proposed protocol for reliable packet delivery in low-power IoT applications. - Justin B. Goins; Ankur Guha Roy; Kartikeya Mayaram; Terri S. Fiez (WF-IoT, 2016)

Fast start-up analysis of resonator based oscillators using a power generation method. - Ankur Guha Roy; Kartikeya Mayaram; Terri S. Fiez (IET Circuits Devices Syst., 2016)

A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation. - Siladitya Dey 002; Karthikeyan Reddy; Kartikeya Mayaram; Terri S. Fiez (CICC, 2017)

A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC. - Hamidreza Maghami; Pedram Payandehnia; Hossein Mirzaie; Kartikeya Mayaram; Ramin Zanbaghi; Terri S. Fiez (ISCAS, 2017)

A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC. - Romesh Kumar Nandwana; Saurabh Saxena; Amr Elshazly; Kartikeya Mayaram; Pavan Kumar Hanumolu (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer. - Hamidreza Maghami; Hossein Mirzaie; Pedram Payandehnia; Kartikeya Mayaram; Ramin Zanbaghi; Terri S. Fiez (MWSCAS, 2018)

A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation. - Siladitya Dey 002; Karthikeyan Reddy; Kartikeya Mayaram; Terri S. Fiez (IEEE J. Solid State Circuits, 2018)

A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4th order CT-ΔΣ modulator with 2nd order noise-shaping and pipelined SAR-VCO based quantizer. - Siladitya Dey 002; Kartikeya Mayaram; Terri S. Fiez (CICC, 2019)

0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique. - Hamidreza Maghami; Pedram Payandehnia; Hossein Mirzaie; Ramin Zanbaghi; Siladitya Dey 002; Justin B. Goins; Kartikeya Mayaram; Terri S. Fiez (CICC, 2019)

A Highly Linear OTA-Free VCO-Based 1-1 MASH $ Delta Sigma$ ADC. - Hamidreza Maghami; Pedram Payandehnia; Hossein Mirzaie; Ramin Zanbaghi; Siladitya Dey 002; Kartikeya Mayaram; Terri S. Fiez (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $ Delta Sigma$ Modulator With Inherent DWA. - Hossein Mirzaie; Hamidreza Maghami; Ramin Zanbaghi; Pedram Payandehnia; Kartikeya Mayaram; Terri S. Fiez (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique. - Hamidreza Maghami; Pedram Payandehnia; Hossein Mirzaie; Ramin Zanbaghi; Hossein Zareie; Justin B. Goins; Siladitya Dey 002; Kartikeya Mayaram; Terri S. Fiez (IEEE J. Solid State Circuits, 2020)