Package and Chip Accelerated Aging Methods for Power MOSFET Reliability Evaluation. - Ting-You Lin; Chauchin Su; Chung-Chih Hung; Karuna Nidhi; Chily Tu; Shao-Chang Huang (DATE, 2019)

Analyzing Gate-Driven Circuit Parameters for Adding ESD Performances. - Shao-Chang Huang; Chih-Cherng Liao; Hsien-Feng Liao; Shou-Peng Weng; Karuna Nidhi; Yu-Kai Wang; Yi-Jen Chen; Hwa-Chyi Chiou; Yeh-Ning Jou; Jian-Hsing Lee (ICCE-TW, 2019)

Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-µm BCD Process. - Chao-Yang Chen; Jian-Hsing Lee; Karuna Nidhi; Tzer-Yaa Bin; Geeng-Lih Lin; Ming-Dou Ker (IRPS, 2021)