A 7-bit 1.75-GS/s 6.9-fJ/conv.-step FoMw Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a 224-Gb/s SerDes Receiver. - Chakravarti Bheemisetti; Karunanidhan Pandey; Idan Lotan; Gadi Ori; Ahmad Khairi; Yoel Krupnik; Udi Virobnik; Subrahmanyam Boyapati; Ariel Cohen 001; Nagendra Krishnapura (IEEE J. Solid State Circuits, 2025)